MA31750 Datasheet, PDF (24/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
CLKOUT
Wait 1
Wait 2
AS
MPROEN
EXADEN
WRN
DSN
SNEW
50
51
50
51
Notes:
Diagram shows a WRITE cycle but is also applicable to READ cycles.
Cycle 'Wait 1' is introduced by MPROEN low.
Cycle 'Wait 2' is introduced by EXADEN low.
Strobes RDN/WRN and DSN are not asserted until faults are clear.
If either MPROEN or EXADEN remains low for two successive falling
edges of TCLK, the relevant fault is logged in the fault register.
Figure 23a: MPROEN and EXADEN Timings
CLKOUT
TCLK
AS
MPROEN
OR
EXADEN
BUSFAULTN
WRN
DSN
SNEW
1
2
Busfault timeout
occurs here.
38
39
54
Strobes suppressed
Notes:
Bus fault timeout occurs after two consecutive TCLK falling edges.
Strobes are suppressed for the duration of the erroneous cycle.
Normal operation resumes with the following cycle.
Figure 23b: Bus Fault Timeout
24/42