MA31750 Datasheet, PDF (36/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
P in Na me Func t ion
Description
MMU CONTROL
AS[0:3]
Address State This active-high bus indicates the current address state of the CPU. The value on this bus
Active HIGH
is copied from the Status Word register within the CPU. These lines are inputs during bus
AS0 is MSB
cycles not assigned to this CPU, so that the MFPR and the MFAR can store the relevant
failure information if a remote failure occurs.
PB[0:3]
Page Bank Select In 1750B mode, this active-high bus indicates the current CPU Page Bank. The value on
Active HIGH
this bus is copied from the Status Word register within the CPU. These lines are inputs
PB0 is MSB
during bus cycles not assigned to this CPU, so that the MFPR and the MFAR can store the
relevant failure information if a remote failure occurs.
DI SCRETES
CONFWN Configuration This active-low output signal is driven low when the processor reads the external
Register Read configuration register. The line may be used as an output enable for this register. The
Strobe
configuration register is read during initialisation and during the execution of a BPT
Active LOW
instruction to determine the system configuration.
SNEW
Start of New
This active-high output will be asserted high during the first phase of each machine cycle.
Cycle Strobe
Active HIGH
DISCON
Discretes Output This active-low output will be asserted low by the processor during an XIO OD or XIO RDOR
Strobe
command. It may be used as the enable signal for an external discrete output register.
Active LOW
DMAE
DMA Enable
This active-high output indicates that an external DMA device is enabled. It is disabled
Active HIGH
(low) following reset and can be toggled under program control using XIO DMAE and XIO
DMAD, (if a DMA device is set as present in the configuration register).
CONREQN Console Request This active-low input initiates and controls Console operation following the end of a 1750
Active LOW
instruction. Commands and data are passed to the processor in this mode via three
dedicated registers in IO space. Console operation takes precedence over Interrupts.
SUREN
Start-Up-ROM This active-low output indicates that start-up ROM is enabled. The signal is asserted low
Enable
following initialisation or by XIO ESUR. The signal remains asserted until removed with XIO
Active LOW
DSUR. When a start-up ROM is present on the system indicated in the configuration word,
this signal should be used to qualify its chip select or output enable such that the ROM
may be accessed only when SUREN is low.
Not e : Instruction pipelining must be considered in moving from Start-Up ROM to RAM.
See Section 4 on Software Considerations.
NPU
Normal Power-Up This output is asserted to indicate that the Built-ln-Test (BIT), performed on reset or power-
Discrete
up, has passed. The line is asserted low following an external reset and may also be reset
Active HIGH
by software using the XIO RNS command.
TGON
Trigger-Go Output This active-low output is asserted low whenever the Trigger-Go counter overflows (rolls
Discrete
over to 0000). It returns to the high state when the counter is reset by software (using the
Active LOW
XIO GO command).
DTON
Disable Timeout A low on this input will reset and disable the bus fault timeout circuit.
Active LOW
DPARN
Disable Parity A low on this input will reset and disable the on-chip parity verification.
Active LOW
Not e : Parity generation on write data is not disabled by this pin.
RESETN CPU reset
This active-low input should be asserted low to reset the processor. The low to high
Reset=LOW
transition will start the initialisation sequence which will perform a Built-In-Test (if
selected), initialising the processor in accordance with MIL-STD-1750 (see figures 2 and 3).
Figure 39 (continued): Pin Descriptions
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