MA31750 Datasheet, PDF (1/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

Replaces July 1999 version, DS3748-7.0
MA^M3^A1³7¹⁷5⁵0⁰
High Performance MIL-STD-1750 Microprocessor
DS3748-8.0 January 2000
The Dynex Semiconductor MA31750 is a single-chip
microprocessor that implements the full MIL-STD-1750A
instruction set architecture, or Option 2 of Draft MIL-STD-
1750B. The processor executes all mandatory instructions and
many optional features are also included. Interrupts, fault
handling, memory expansion, Console, timers A and B, and
their related optional instructions are also supported in full
accordance with MIL-STD-1750.
The MA31750 offers a considerable performance increase
over the existing MAS281. This is achieved by using a 32-bit
internal bus structure with a 24 x 24 bit multiplier and 32-bit
ALU. Other performance-enhancing features include a 32-bit
shift network, a multi-port register file and a dedicated address
calculation unit.
The MA31750 has on-chip parity generation and checking
to enhance system integrity. A comprehensive built-in self-test
has also been incorporated, allowing processor functionality to
be verified at any time.
Console operation is supported through a parallel interface
using command/data registers in l/O space. Several discrete
output signals are produced to minimise external logic.
Control signals are also provided to allow inclusion of the
MA31750 into a multiprocessor or DMA system.
The processor can directly access 64KWords of memory in
full accordance with MIL-STD-1750A. This increases to
1MWord when used with the optional MA31751 memory
management unit (MMU). 1750B mode allows the system to
be expanded to 8MWord with the MMU.
Bus
Parity arb.
Bus
Control ^{Address Data}
C0
IO control
C1
IC
A
DOUT
X
IB
Address
BR
Register
generator
IA
file
rap
CLK
ebf
uAddr
Microcode ROM
Sequencer
Microcode control
words to other blocks
uData
ALU
Qshift
sc
Multiplier
ir
Shift network
abort
Interrupt
controller
R bus
S bus
Ints
Faults
INTAKN
BUSFAULTN
mov
bf
aluv
Flags
Y bus
Figure 1: Architecture
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