MA31750 Datasheet, PDF(21/42 Page) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

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MA31750 Datasheet, PDF (21/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

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MA31750

5.4 I/O COMMAND SUMMARY

Operation

Mnem Code Ext1

I mple me nt e d in CP U

1 7 5 0 A or B mode

Set Interrupt Mask

Clear Interrupt Request

Enable Interrupts

Disable Interrupts

Reset Pending Interrupt

Set Pending Interrupt Reg.

Write Output Discrete Reg.

Reset Normal Power Up Line

Write Status Word

Enable Start-Up ROM 3

Disable Start-Up ROM 3

Direct Memory Access Enable3

Direct Memory Access Disable3

Timer A Start

Timer A Halt

Output Timer A

Reset Trigger-Go

Timer B Start

Timer B Halt

Output Timer B

Read Interrupt Mask

Read Pending Interrupt Reg.

Read Output Discrete Reg.

Read Status Word

Read and Clear Fault Reg.

Input Timer A

Input Timer B

Read Memory Fault Status

GPS Defined XI Os

Set Fault Register

Load OAS register

Output Trigger-Go Reset Reg.

Write Page Bank Select

Read Fault Register (No clear)

Read Linkage Pointer

Read Processor Status

Read OAS register

Read Memory Fail Address

Read Memory Fail Page

Read Internal Config. Word

Run Built In Test

Input Trigger-Go Reset Reg.

Read External Configuration

SMK

CLIR

ENBL

DSBL

RPI

SPI

OD

RNS

WSW

ESUR

DSUR

DMAE

DMAD

TAS

TAH

OTA

GO

TBS

TBH

OTB

RMK

RPIR

RDOR

RSW

RCFR

ITA

ITB

RMFS

2000 No

2001 No

2002 No

2003 No

2004 No

2005 No

2008 Yes

200A No

200E Yes

4004 No

4005 No

4006 No

4007 No

4008 No

4009 No

400A No

400B No

400C No

400D No

400E No

A000 No

A004 No

A008 Yes

A00E No

A00F No

C00A No

C00E No

A00D No

SFR

LOS

OTGR

WPBS

RFR

RLP

RPS

ROS

RMFA

RMFP

ICW

BIT

ITGR

RCW

0401 No

0406 No

040E No

200C No

8401 No

8404 No

8405 No

8406 No

8407 No

8408 No

840C No

840D No

840E No

8410 Yes

Implemented in CPU,

1750B mode only.

Output Timer A Reset Reg.

Output Timer B Reset Reg.

Input Timer A Reset Register 2

Input Timer B Reset Register 2

Set Fault Mask

Write Page Bank Select

Read Page Bank Select

Read Fault Mask

OTAR

OTBR

ITAR

ITBR

SFMK

WPBS

RPBS

RFMK

4002 No

400F No

C002 No

C00F No

2006 No

200F No

A00C No

A006 No

Implemented in BPU

Memory Protect Enable3

Load Memory Protect RAM 3

Read Memory Protect RAM 3

Load Ext Mem. Protect RAM 3,5

Read Ext. Mem. Protect RAM 3,5

MPEN

LMP

RMP

LXMP

RXMP

4003 Yes

50XX Yes

D0XX Yes

4XXX Yes

CXXX Yes

Implemented in MMU

Write Instruction Page Reg.3

Write Operand Page Reg. 3

Read Instruction Page Reg.3

Read Operand Page Reg. 3

WIPR

WOPR

RIPR

ROPR

51XY Yes

52XY Yes

D1XY Yes

D2XY Yes

Implemented in Console 6

Console Data Output 4

CO

Console Command 4

CC

Console Data Input 4

CI

4000 Yes

8402 Yes

C000 Yes

Reserved by GPS

(Unavailable to the user)

Initialise Interrupt Logic

Set NPU

Write Internal config word

Write Memory Config. Reg.

FMCR

PINIT

RNPU

WCW

WMCR

FMCR

0403 No

040A No

040C No

0400 Yes

A010 No

Spare and Reserved

Output

Input

04XX-1FXX 84XX-9FXX

21XX-2fXX A1XX-AFXX

30XX-3FXX B0XX-BFXX

41XX-4FXX C1XX-CFXX

53XX-7FXX D3XX-FFXX

Addresses

Spare

Reserved

Spare

Reserved

Spare

1 External cycles output on the address bus

2 GPS defined 1750B XIOâs Reserved Addresses

3 Command illegal if device not implemented in config word

4 External cycle needing external ready generation

5 Only implemented in 1750B

6 The address 4001 and C001 are implemented but have no

effect in the 31750.

Figure 20c: Internal I/O Command Summary

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