IBIS4-A-6600 Datasheet, PDF (9/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
Sensor Architecture and Operation
Floor Plan
Figure 3. Floor Plan
S E NS OR
IMAGE C OR E
IBIS4-A-6600
CYII4SM6600AB
pixel array
2210 x 3002
(excl. dark +
dummy pixels )
P ixel (0,0)
clk_x
s ync_x
column amplifiers
addres s able x-s hift regis ter + s ub-s ampling
addres s &
data bus
Dig. logic
DAC
SPI
DAC in
Dig. logic
analog output (2)
Floor Plan on page 9 shows the architecture of the image
sensor that has been designed. It consists basically of the pixel
array, shift registers for the readout in x and y direction, parallel
analog output amplifiers, and column amplifiers that correct for
the fixed pattern noise caused by threshold voltage
non-uniformities. Reading out the pixel array starts by applying
a y clock pulse to select a new row, followed by a calibration
sequence to calibrate the column amplifiers (row blanking
time). Depending on external bias resistors and timing,
typically this sequence takes about 7 s per line (baseline). This
sequence is necessary to remove the Fixed Pattern Noise of
the pixel and of the column amplifiers themselves (by means
of a Double Sampling technique). Pixels can also be read out
in a non-destructive manner. Two DACs have been added to
make the offset level of the pixel values adjustable and equal
for the two output busses. A third DAC is used to connect the
busses to a stable voltage during the row blanking period (or
to the reset busses continuously in case of non-destructive
readout). Two 10-bit ADCs running at 20 Msamples/s will
convert the analog pixel values. The digital outputs will be
multiplexed to 1 digital 10-bit output at 40 Msamples/s. Note
that these blocks are electrically completely isolated from the
sensor part (except for the multiplexer for which the settings
are uploaded through the shared address and data bus).
The x and y shift registers do have a programmable starting
point. The starting point's possibilities are limited due to
limitations imposed by sub-sampling requirements. The
upload of the start address is done through the serial to parallel
interface.
Most of the signals for the image core in Floor Plan on page 9
are generated on chip by the sequencer. This sequencer also
allows running the sensor in basic modes, not fully
autonomously.
Document Number: 001-02366 Rev. *D
Page 9 of 40
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