IBIS4-A-6600 Datasheet, PDF (13/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
IBIS4-A-6600
CYII4SM6600AB
Stage 3: Output Drivers
Offset DACs
The speed and power consumption of the third stage is
controllable through the resistor connected to CMD_OUT_3.
The output drivers are designed to drive a 20-pF output load
at 40 Msamples/s with a bias resistor of 100 k?.
Figure 9. shows how the DAC registers influence the black
reference voltages of the two different channels. The offset is
mainly given through DAC_raw. DAC_fine can be used to shift
the reference voltage of bus 2 up or down to compensate for
different offsets in the two channels.
Figure 9. Offset for the Two Channels through DAC_RAW and DAC_FINE
DAC_RAW_REG<0:7
DAC_raw
out
10K
200K
blackref
bus1
RCAL
+ _VCAL
rcal
pad RCAL_DAC_OUT
VDDA
50K
10K
blackref
bus2
DAC_FINE_REG<0:7
DAC_fine
out
rcal
floating
GNDA
50K
200K
Assume that Voutfull is the voltage that depends on the bit
values that are applied to the DAC and ranges from
V_outfull : 0 (bit values 00000000 )
o
VDDA (1 
1
2⁸
)
(bit values 11111111 )
Externally, the output range of DAC_raw can be changed by
connecting a resistor Rcal to RCAL_DAC_OUT and applying
a voltage Vcal. The output voltage Vout of DAC_raw follows
relation (R = 10 kΩ)
V_out
R  R_cal
2R  R_cal
V_outfull

2R
R
 R_cal
V_cal
Special case:
Rcal = then Vout = Voutfull (e.g. for DAC_fine)
Rcal = 0, Vcal = GND........................... then Vout = Voutfull/2
A similar relation holds for the output range of DAC_DARK
(RCAL_DAC_DARK can be used to tune the output range of
this DAC).
Analog to Digital Converter
The IBIS4-6600 has a two 10 bit flash analog digital
converters. The ADC's are electrically separated from the
image sensor. The inputs of the ADC should be tied externally
to the outputs of the output amplifiers. One ADC will sample
the even columns and the other one will sample the odd
columns. Alternatively, one ADC can sample all the pixels as
well.
Table 10. ADC specifications
Parameter
Specification
Input range
Set by external resistors
(see next section)
Quantization
10 Bits
Nominal data rate
20Msamples/s
DNL(Linear conversion mode) Typ. < 0.4LSB RMS
INL (linear conversion mode) Typ. < 3.5 LSB
Input capacitance
< 2 pF
Conversion law
Linear/Gamma-corrected
Document Number: 001-02366 Rev. *D
Page 13 of 40
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