IBIS4-A-6600 Datasheet, PDF (24/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
IBIS4-A-6600
CYII4SM6600AB
synchronize them to the real pixel values at the analog output
or the ADC output (which give additional delays depending on
their settings). The bit settings and corresponding delay is
indicated in Table 18. .
Table 18. Delay added by Changing the Settings of the DELAY Register
bits
0000
0001
0010
0011
0100
0101
0110
0111
Delay [# SYS_CLOCK periods]
0
0
0
1
2
3
4
5
bits
1000
1001
1010
1011
1100
1101
1110
1111
Delay [# SYS_CLOCK periods]
6
7
8
9
10
11
12
13
X_REG Register
The X_REG register determines the start position of the
window in the X-direction. In this direction, there are 2208 + 2
+ 12 readable pixels. In the active pixel array sub-sampling
blocks are 24 pixels wide and the columns are read two by two
and therefore, the number of start positions equals 2208/24
+2/2 +12/2 = 92 + 1 + 6 = 99.
Y_REG Register
The Y_REG register determines the start position of the
window in the Y-direction. In this direction, there are 3000 + 2
+ 12 readable pixels. In the active pixel array sub-sampling
blocks are 24 pixels wide and the rows are read one by one
and therefore, the number of start positions equals 3000/24 +
2/2 +12 = 125 + 1 + 12 = 138.
Image_core Register
Bits 0:1 of the IMAGE_CORE register defines the several test
modes of the image core. Setting 00 is the default and normal
operation mode. In case the bit is set to 1, the odd (bit 0) or
even (bit 1) columns are tight to VDD. These test modes can
be used to tune the sampling point of the ADCs to an optimal
position.
Bits 2:7 of the IMAGE_CORE register define the sub-sampling
mode in the X-direction (bits 2:4) and in the Y-direction (bits
5:7). The sub-sampling modes and corresponding bit setting
are given in Analog to Digital Converter on page 13
AMPLIFIER Register
a. Gain (bits 0:3)
The gain bits determine the gain setting of the output amplifier.
They are only effective if UNITY = 0. The gains and
corresponding bit setting are given in Table 9. Stage 2:
Programmable Gain Amplifier on page 12.
b. Unity (bit 4)
In case UNITY = 1, the gain setting of GAIN is bypassed and
the gain amplifier is put in unity feedback.
c. One_out
If ONE_OUT = 0, the two output amplifiers are active. If
ONE_OUT = 1, the signals from the two busses are
multiplexed to output OUT1. The gain amplifier and output
driver of the second path are put in standby.
d. Standby
If STANDBY = 1, the complete output amplifier is put in
standby (this reduces the power consumption significantly)
e. Delay_clk_amp
The clock that acts on the output amplifier can be delayed to
compensate for any delay that is introduced in the path from
shift register, column selection logic, column amplifier and
busses to the output amplifier. Setting '000' is used as a
baseline.
Table 19. Delay added by Changing the Settings of the
DELAY_CLK_AMP Bits
Bits
Delay [ns]
Bits
Delay [ns]
000
1.7
100
Inversion + 8.3
001
2.9
2.9
Inversion + 9.7
010
4.3
110
Inversion + 11.1
011
6.1
111
Inversion + 12.3
Dac_raw_reg and Dac_fine_reg Register
These registers determine the black reference level at the
output of the output amplifier. Bit setting 11111111 for
DAC_RAW_REG register gives the highest offset voltage; bit
setting 00000000 for DAC_RAW_REG register gives the
lowest offset voltage. Ideally, if the two output paths have no
offset mismatch, the DAC_FINE_REG register must be set to
10000000. Deviation from this value can be used to
compensate the internal mismatch (see Offset DACs on page
13).
Dac_raw_dark Register
This register determines the voltage level that is put on the
internal busses during calibration of the output stage. This
voltage level is also continuously put on the reset busses in
case of non-destructive readout (as a reset level for the double
sampling FPN correction).
Document Number: 001-02366 Rev. *D
Page 24 of 40
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