IBIS4-A-6600 Datasheet, PDF (12/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
IBIS4-A-6600
CYII4SM6600AB
Output Amplifier
The output amplifier subtracts the reset and signal voltages
from each other to cancel FPN as much as possible (Figure
8.). The DAC that is used for offset adjustment consists of 2
DACs. One is used for the main offset (DAC_raw) and the
other allows for fine tuning to compensate the offset difference
between the signal paths arriving at the two amplifiers A1 and
A2 (DAC_fine). With the analog multiplexer the signals S1 and
S2 from the two busses can be combined to one pixel output
at full pixel rate (40 MHz). The two analog signals S1 and S2
can, however, also be available on two separate output pins to
allow a higher pixel rate.
The third DAC (DAC_dark) puts its value on the busses during
the calibration of the output amplifier. In case of
non-destructive readout (no double sampling), bus1_R and
bus2_R are continuously connected to the output of the
DAC_fine to provide a reference for the signals on bus1_S and
bus2_S.
The complete output amplifier can be put in standby by setting
the corresponding bit in the AMPLIFIER register.
Figure 8. Output Amplifier Architecture
bus1 S
bus1_R
+
A1
S1

analog
multiplexer
programmable
gain amplifiers
output
drivers
1
Pixel output
bus2 S
bus2_R
+
A2
S2

Pixel output 2
1
DAC_raw /
DAC_fine
Stage 1
Stage 2
Stage 3
DAC_dark
Stage 1: Offset, FPN Correction and Multiplexing
In the first stage, the signals from the busses are subtracted
and the offset from the DACs is added. After a system reset,
the analog multiplexer is configured for two outputs (see bit
settings of the AMPLIFIER register). In case ONE_OUT is set
to 1, the two signals S1 and S2 are multiplexed to one output
(output 1). The amplifiers of stage 2 and stage 3 of the second
output path are then put in standby. The speed and power
consumption of the first stage is controllable through the
resistor connected to CMD_OUT_1.
Stage 2: Programmable Gain Amplifier
The second stage provides the gain, which will be adjustable
between 1.36 and 17.38 in steps of roughly 20.25 (~1.2). An
overview of the gain settings is given in Table 9. . The speed
and power consumption of the second stage is controllable
through the resistor connected to CMD_OUT_2.
Table 9. PGA Gain Settings
Bits
0000
0001
0010
0011
0100
0101
0110
0111
DC Gain
1.36
1.64
1.95
2.35
2.82
3.32
3.93
4.63
Bits
1000
1001
1010
1011
1100
1101
1110
1111
DC Gain
5.40
6.35
7.44
8.79
10.31
12.36
14.67
17.38
Document Number: 001-02366 Rev. *D
Page 12 of 40
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