IBIS4-A-6600 Datasheet, PDF (22/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
IBIS4-A-6600
CYII4SM6600AB
These bits only influence the operation of the sensor in case
NDR (bit 0) is set to 1. There are basically two modes for
non-destructive readout (mode 1 and 2). Each mode needs
two different frame readouts (setting 1 and 2 for mode 1,
setting 3 and 4 for mode 2). First a reset/readout sequence
(called reset_seq hereafter) and then one or several pure
readout sequences (called read_seq hereafter). Table 16.
gives an overview of the different NDR modes.
Table 16. Overview of NDR Modes.
Setting
1
2
3
4
Bits
NDR mode
00
1
01
1
10
2
11
2
Sequence
reset
read
reset
read
Mode 1
In this mode, the sensor is readout in the same way as for
non-destructive readout. However, electronic shutter control is
not possible in this case, i.e., the minimal (integration) time
between two readings is equal to the number of lines that has
to be read out (frame read time). The row lines are clocked
simultaneously (left and right clock pulses are equal).
Mode 2
In mode 2, it is possible to have a shorter integration time than
the frame read time. Rows are alternating read out with the left
and right pointer. These two pointers can point to two different
rows (see INT_TIME register). The (integration) time between
two readings of the same row is equal to the number of lines
that is set in the INT_TIME register times 2 plus 1 and is
minimal 1 line read time. In setting 3, the row that is read out
by the left pointer is reset and read out (first Y_CLOCK), the
row that is read out by the right pointer is read out without
resetting (second Y_CLOCK). In setting 4, both rows are read
out without resetting (on the first Y_CLOCK the row is read out
by the left pointer; on the second Y_CLOCK the row is read
out by the right pointer).
For both modes, the signals are read out through the same
path as with destructive readout (double sampling) but the
busses that are carrying the reset signals in destructive
readout, are in non-destructive readout set to the voltage given
by DAC_DARK.
c. Reset_black (bit 3)
If RESET_BLACK is set to 1, each line is reset before it is read
out (except for the row that is read out by the right pointer in
NDR mode 2). This might be useful to obtain black pixels.
d. Fast_reset (bit 4)
The fast reset option (FAST_RESET = 1) might be useful in
case a mechanical camera shutter is used. The fast reset is
done on a row-by-row basis, not by a global reset. A global
reset means charging all the pixels at the same time, which
may result in a huge peak current. Therefore, the rows can be
scanned rapidly while the left and right shift registers are both
controlled identically, so that the reset lines over the pixel array
are driven from both sides. This reduces the reset (row
blanking) time (when FAST_RESET = 1 the smallest
X-granularity can be used). After the row blanking time the row
is reset and Y_CLOCK can be asserted to reset the next row.
After a certain integration time, the read out can be done in a
similar way. The Y shift registers are again synchronized to the
first row. Both shift registers are driven identically, and all rows
& columns are scanned for (destructive) readout.
FAST_RESET = 1 puts the sequencer in such mode that the
left and right shift registers are both controlled identically.
e. Output amplifier calibration (bit 5 and 6)
Bits FRAME_CAL_MODE and LINE_CAL_MODE define the
calibration mode of the output amplifier.
During every row-blanking period, a calibration is done of the
output amplifier. There are 2 calibration modes. The FAST
mode (= 0) can force a calibration in one cycle but is not so
accurate and suffers from kTC noise, while the SLOW mode
(= 1) can only make incremental adjustments and is noise free.
Approximately 200 or more "slow" calibrations will have the
same effect as 1 "fast" calibration.
Different calibration modes can be set at the beginning of the
frame (FRAME_CAL_MODE bit) and for every subsequent
row that is read (LINE_CAL_MODE bit).
f. Continuous charge (bit 7)
For some applications it might be necessary to use continuous
charging of the pixel columns instead of a precharge on every
row sample operation.
Setting bit CONT_CHARGE to 1 will activate this function. The
resistor connected to pin CMD_COL is used to control the
current level on every pixel column.
g. Internal clock granularities
The system clock is divided several times on-chip.
The X-shift-register that controls the column/pixel readout, is
clocked by half the system clock rate. Odd and even pixel
columns are switched to 2 separate busses. In the output
amplifier the pixel signals on the 2 busses can be combined to
one pixel stream at 40 MHz.
The clock that drives the X-sequencer can be a multiple of 2,
4, 8 or 16 times the system clock. Table 17. gives the settings
for the granularity of the X-sequencer clock and the
corresponding row blanking time (for NDR = 0). A row blanking
time of 7.18 µs is the baseline for almost all applications
Document Number: 001-02366 Rev. *D
Page 22 of 40
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