IBIS4-A-6600 Datasheet, PDF (29/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
IBIS4-A-6600
CYII4SM6600AB
Pin List
Table 20. is a list of all the pins and their function. In total,
there are 68 pins. All pins with the same name can be
connected together.
Table 20. Pin List
Pin
1
2
Pin Name
CMD_COL_CTU
CMD_COL
Pin Type
Input
Input
3
CMD_COLAMP
Input
4
CMD_COLAMP_CTU Input
5
RCAL_DAC_DARK Input
6
RCAL_DAC_OUT
7
VDDA
8
GNDA
9
VDDD
10
GNDD
11
CMD_OUT_1
Input
Power
Power
Power
Power
Input
12
CMD_OUT_2
Input
13
CMD_OUT_3
Input
14
SPI_CLK
15
SPI_DATA
16
VDDAMP
17
CMD_FS_ADC
18
CMD_SS_ADC
19
CMD_AMP_ADC
20
GNDAMP
21
OUT1
Input
Input
Power
Input
Input
input
Ground
Output
22
ADC_IN1
23
VDDAMP
Input
Power
Expected Voltage
[V]
0
1.08
0.66
0.37
1.27 @ code 128
DAC_DARK reg
0
2.5
0
2.5
0
0.78
0.97
0.67
-
-
2.5
0.73
0.73
0.59
0
Black level: 1 @
code 190
DAC_RAW reg.
See OUT1.
2.5
Pin Description
Biasing of columns (ctu). Decouple with 100 nF to GNDA.
Biasing of columns. Connect to VDDA with R = 10 k and
decouple to GNDA with C = 100 nF.
Biasing of column amplifiers. Connect to VDDA with R =
100 k and decouple to GNDA with C = 100 nF.
Biasing of column amplifiers. Connect to VDDA with R =
10 M and decouple to GNDA with C = 100 nF.
Biasing of DAC for dark reference. Can be used to set
output range of DAC.
Default: decouple to GNDA with C = 100 nF.
Biasing of DAC for output dark level. Can be used to set
output range of DAC. Default: connect to GNDA.
VDD of analog part [2.5V].
GND (&substrate) of analog part.
VDD of digital part [2.5V].
GND (&substrate) of digital part.
Biasing of first stage output amplifiers. Connect to
VDDAMP with R = 50 k and decouple to GNDAMP with
C = 100 nF.
Biasing of second stage output amplifiers. Connect to
VDDAMP with R = 25 k and decouple to GNDAMP with
C = 100 nF.
Biasing of third stage output amplifiers. Connect to
VDDAMP with R = 100 k and decouple to GNDAMP with
C = 100 nF.
Clock of digital parameter upload. Shifts on rising edge.
Serial address and data input. 16 bit word. Address first.
MSB first.
VDD of analog output [2.5V] (Can be connected to
VDDA).
Biasing of first stage ADC. Connect to VDDA_ADC with
R = 50 k and decouple to GNDA_ADC with C = 100 nF.
Biasing of second stage ADC. Connect to VDDA_ADC
with R = 50 k and decouple to GNDA_ADC.
Biasing of input stage ADC. Connect to VDDA_ADC with
R = 180 k and decouple to GNDA_ADC with C = 100 nF.
GND (&substrate) of analog output.
Analog output 1.
Analog input ADC 1.
VDD of analog output [2.5V] (Can be connected to
VDDA).
Document Number: 001-02366 Rev. *D
Page 29 of 40
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