IBIS4-A-6600 Datasheet, PDF (25/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
IBIS4-A-6600
CYII4SM6600AB
ADC Register
f. Delay_clk_adc
a. Standby_1 and standby_2
In case only one or none of the ADCs is used, the other or both
ADCs can be put in standby by setting the bit to 1 (this reduces
the power consumption significantly).
b. One
In case OUT1 and OUT2 are both used and connected to
ADC_IN1 and ADC_IN2 respectively, ONE must be 0 to use
both ADCs and to multiplex their output to ADC_D<9:0>. If
ONE = 1, the multiplexing is disabled.
The clock that finally acts on the ADCs can be delayed to
compensate for any delay that is introduced in the path from
the analog outputs to the input stage of the ADCs. The same
settings apply as for the delay that can be given to the clock
acting on the output amplifier (see Table 19. ). The best
setting will also depend on the delay of the output amplifier
clock and the load of the output amplifier. It must be used to
optimize the sampling moment of the ADCs with respect to the
analog pixel input signals. Setting '000' is used as a baseline.
g. Gamma
c. Switch
In case the two ADCs are used (ONE = 0) and internal pixel
clock (EXT_CLK = 0), the ADC output is delayed with one
system clock cycle if SWITCH = 1. In case the two ADCs are
used (ONE = 0) and an external ADC clock (EXT_CLK = 1) is
applied, the ADC output is delayed with half ADC clock cycle
if SWITCH = 1.
In case only one ADC is used, the digital multiplexing is
disabled by ONE = 1, but SWITCH selects which ADC output
is on ADC_D<9:0> (SWITCH = 0: ADC_1, SWITCH = 1:
ADC_2).
d. Ext_clk
In case EXT_CLK = 0, the internal pixel clock (that drives the
X-shift registers and output amplifier, i.e. half the system clock)
is used as input for the ADC clock. In case EXT_CLK = 1, an
external clock must be applied to pin ADC_CLK_EXT (pin 46).
e. Tristate
In case TRISTATE = 1, the ADC_D<9:0> outputs are in
tri-state mode.
If GAMMA is set to 0, the ADC input to output conversion is
linear, otherwise the conversion follows a 'gamma' law (more
contrast in dark parts of the window, lower contrast in the bright
parts).
h. Bitinvert
If BITINVERT = 0, 0000000000 is the conversion of the lowest
possible input voltage, otherwise the bits are inverted.
Serial to Parallel Interface
To upload the sequencer registers a dedicated serial to parallel
interface (SPI) is implemented. 16 bits (4 address bits + 12
data bits) must be uploaded serially. The address must be
uploaded first (MSB first), then the data (also MSB first).
The elementary unit cell is shown in Figure 18. 16 of these
cells connected in series, having a common SPI_CLK form the
entire uploadable parameter block, where Dout of one cell is
connected to SPI_DATA of the next cell (max. speed 20 MHz).
The uploaded settings on the address/data bus are loaded into
the correct register of the sensor on the rising edge of signal
REG_CLOCK and become effective immediately.
Figure 18. SPI Interface
16 outputs to address/data bus
REG_CLOCK
SPI_DATA
SPI_CLK
D
Q
SPI_DATA
SPI_CLK
C
To address/data bus
REG_CLOCK
D
Q
Dout
C
SPI_CLK
E ntire uploadable addres s block
Unity C ell
SPI_DATA
REG_CLOCK
A3
A2
A1
D0
Internal register
upload
Document Number: 001-02366 Rev. *D
Page 25 of 40
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