IBIS4-A-6600 Datasheet, PDF (28/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
IBIS4-A-6600
CYII4SM6600AB
Figure 22. Pixel Output Timing Multiplexing to One Analog Output
ADC Timing
Two Analog Outputs
Figure 23. ADC Timing using Two Analog Outputs
Figure 23. shows the timing of the ADC using two analog
outputs. Internally, the ADCs sample on the falling edge of the
ADC_CLOCK (in case of internal clock, the clock is half the
SYS_CLOCK).
T1: Each ADC has a pipeline delay of 2 ADC_CLOCK cycles.
This results in a total pipeline delay of 4 pixels.
One Analog Output
Figure 24. ADC Timing using One Analog Output
Figure 24. shows the timing of the ADC using one analog
output. Internally, the ADC samples on the falling edge of the
ADC_CLOCK.
T1: The ADC has a pipeline delay of 2 ADC_CLOCK cycles.
Document Number: 001-02366 Rev. *D
Page 28 of 40
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