IBIS4-A-6600 Datasheet, PDF (23/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
IBIS4-A-6600
CYII4SM6600AB
.
Table 17. Granularity of X-Sequencer Clock and Corresponding Row Blanking Time (for NDR = 0).
Gran_x_seq_msb/lsb
00
01
10
11
X-sequencer clock
2 x sys_clock
4 x sys_clock
8 x sys_clock
16 x sys_clock
Row blanking time
142 x TSYS_CLOCK
282 x TSYS_CLOCK
562 x TSYS_CLOCK
1122 x TSYS_CLOCK
Row blanking time [µs]
3.55
7.05
14.05
1122 x TSYS_CLOCK
h. Black (bit 10)
k. Nrof_lines Register
In case BLACK is set to 1, the internal black signal will be held
high continuously. As a consequence, the column amplifiers
are disconnected from the busses, the busses are set to the
voltage given by DAC_DARK and the output of the amplifier
equals the voltages from the offset DACs.
i. Reset_all (bit 11)
In case RESET_ALL is set to 1, all the pixels are
simultaneously put in a 'reset' state. In this state, the pixels
behave logarithmically with light intensity. If this state is
combined with one of the NDR modes, the sensor can be used
in a non-integrating, logarithmic mode with high dynamic
range.
j. Nrof_pixels Register
After the internal X_SYNC is generated (start of the pixel
readout of a particular row), the PIXEL_VALID signal goes
high. The PIXEL_VALID signal goes low when the pixel
counter reaches the value loaded in the NROF_PIXEL register
and an EOL pulse is generated. Due to the fact that 2 pixels
are addressed at each internal clock cycle the amount of pixels
read out in one row = 2*(NROF_PIXEL + 1).
After the internal YL_SYNC is generated (start of the frame
readout with Y_START), the line counter increases with each
Y_CLOCK pulse until it reaches the value loaded in the
NROF_LINES register and an EOF pulse is generated. In
NDR mode 2, the line counter increments only every two
Y_CLOCK pulses and the EOF pulse shows up only after the
readout of the row indicated by the right shift register
INT_TIME Register
When the Y_START pulse is applied (start of the frame
readout), the sequencer will generate the YL_SYNC pulse for
the left Y-shift register. This loads the left Y-shift register with
the pointer loaded in Y_REG register. At each Y_CLOCK
pulse, the pointer shifts to the next row and the integration time
counter increases (increment only every two Y_CLOCK
pulses in NDR mode 2) until it reaches the value loaded in the
INT_TIME register. At that moment, the YR_SYNC pulse for
the right Y-shift register is generated which loads the right
Y-shift register with the pointer loaded in Y_REG register
(Figure 17.).
Figure 17. Syncing of the Y-shift Registers.
Sync of left
shift-register
Sync of right
shift-register
Last line, followed by
sync of left shift-register
Line n
Sync
Treg_int
Tint
Treg_int: ................ Difference between left and right pointer
. = integration counter until value "n" of INT_TIME register is
reached
..............................................................= INT_TIME register.
In case of NDR = 0, the actual integration time Tint is given by
TintL: ................................................ Integration time [# lines]
..................= NROF_LINES register - INT_TIME register + 1
In case of NDR = 1, NDR mode 1, the time Tint between two
readings of the same row is given by
Tint: .................................................. Integration time [# lines]
...................................................= NROF_LINES register + 1
In case of NDR = 1, NDR mode 2, the times Tint1 and Tint2
between two readings of the same row (alternatingly) are
given by
Tint1:................................................ Integration time [# lines]
....................................................= 2 * INT_TIME register + 1
Tint2:................................................ Integration time [# lines]
= 2 * (NROF_LINES register + 1) - (2 * INT_TIME register + 1)
DELAY register
The DELAY register can be used to delay the PIXEL_VALID
pulse (bits 0:3) and the EOL/EOF pulses (bits 4:7) to
Document Number: 001-02366 Rev. *D
Page 23 of 40
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