IBIS4-A-6600 Datasheet, PDF (31/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
IBIS4-A-6600
CYII4SM6600AB
Table 20. Pin List (continued)
Pin
57
58
59
60
Pin Name
ADC_D<5>
ADC_D<4>
ADC_D<3>
VDD_RESET
Pin Type
Output
Output
Output
Power
61
ADC_D<2>
62
ADC_D<1>
63
ADC_D<0>
64
BS_RESET
Output
Output
Output
Input
65
BS_CLOCK
Input
66
BS_DIN
Input
67
BS_BUS
Output
68
CMD_DEC
Input
Expected Voltage
[V]
-
-
-
2.5
-
-
-
-
-
-
-
0.74
Pin Description
ADC data output.
ADC data output.
ADC data output.
Reset voltage [2.5V]. Highest voltage to the chip. 3.3 V
for extended dynamic range or 'hard reset'.
ADC data output.
ADC data output.
ADC data output (LSB).
Boundary scan (allows debugging of internal nodes):
reset. Tie to GND if not used.
Boundary scan (allows debugging of internal nodes):
clock. Tie to GND if not used.
Boundary scan (allows debugging of internal nodes): in.
Tie to GND if not used.
Boundary scan (allows debugging of internal nodes): bus.
Leave floating if not used.
Biasing of X and Y decoder. Connect to VDDD with R =
50 k? and decouple to GNDD with C = 100 nF.
Note on Power-on Behavior
At power-on, the chip is in an undefined state. It is advised that
the power-on is accompanied by the assertion of the
SYS_CLOCK and a SYS_RESET pulse that puts all internal
registers in their default state (all bits are set to 0). The X-shift
registers are in a defined state after the first X_SYNC which
occurs a few microseconds after the first Y_START and
Y_CLOCK pulse. Prior to this X_SYNC, the chip may draw
more current from the analog power supply VDDA. It is
therefore favorable to have separate analog and digital
supplies. The current spike (if there will be any) may also be
avoided by a slower ramp-up of the analog power supply or by
disconnecting the resistor on pin 3 (CMD_COLAMP) at
start-up.
Document Number: 001-02366 Rev. *D
Page 31 of 40
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