IBIS4-A-6600 Datasheet, PDF (30/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
IBIS4-A-6600
CYII4SM6600AB
Table 20. Pin List (continued)
Pin
Pin Name
24
OUT2
Pin Type
Output
25
ADC_IN2
26
VDDD
27
GNDD
28
GNDA
29
VDDA
30
REG_CLOCK
31
SYS_CLOCK
32
SYS_RESET
33
Y_CLK
34
Y_START
35
GNDD_ADC
36
VDDD_ADC
37
GNDA_ADC
38
VDDA_ADC
39
VHIGH_ADC
Input
Power
Power
Power
Power
Input
Input
Input
Input
Input
Power
Power
Power
Power
Input
40
VLOW_ADC
Input
41
GNDA_ADC
42
VDDA_ADC
43
GNDD_ADC
44
VDDD_ADC
45
VDD_RESET_DS
46
ADC_CLK_EXT
47
EOL
48
EOF
49
PIX_VALID
50
TEMP
51
ADC_D<9>
52
VDD_PIX
53
GND_AB
54
ADC_D<8>
55
ADC_D<7>
56
ADC_D<6>
Power
Power
Power
Power
Power
Input
Output
Output
Output
Output
Output
Power
Power
Output
Output
Output
Expected Voltage
[V]
Black level: 1 @
code 190
DAC_RAW reg.
See OUT2.
2.5
0
0
2.5
-
-
-
-
-
0
2.5
0
2.5
1.5
0.42
0
2.5
0
2.5
2.5 (for no dual
slope)
-
-
-
-
-
-
2.5
0
-
-
-
Pin Description
Analog output 2.
Analog input ADC 2.
VDD of digital part [2.5V].
GND (&substrate) of digital part.
GND (&substrate) of analog part.
VDD of analog part [2.5V].
Register clock. Data on internal bus is copied to
corresponding registers on rising edge.
System clock defining the pixel rate (nominal 40 MHz,
50% +/- 5% duty cycle).
Global system reset (active high).
Line clock.
Start frame readout.
GND (&substrate) of digital part ADC.
VDD of digital part [2.5V] ADC.
GND (&substrate) of analog part.
VDD of analog part [2.5 V].
ADC high reference voltage (e.g. connect to VDDA_ADC
with R = 560 Ω and decouple to GNDA_ADC with C = 100
nF.
ADC low reference voltage (e.g. connect to GNDA_ADC
with R = 220 Ω and decouple to GNDA_ADC with C = 100
nF.
GND (&substrate) of analog part.
VDD of analog part [2.5 V].
GND (&substrate) of digital part ADC.
VDD of digital part [2.5 V] ADC.
Variable reset voltage (dual slope).
External ADC clock.
Diagnostic end of line signal (produced by sequencer),
can be used as Y_CLK.
Diagnostic end of frame signal (produced by sequencer),
can be used as Y_START.
Diagnostic signal. High during pixel readout.
Temperature measurement. Output voltage varies
linearly with temperature.
ADC data output (MSB).
VDD of pixel core [2.5V].
Anti-blooming ground. Set to 1 V for improved
anti-blooming behavior.
ADC data output.
ADC data output.
ADC data output.
Document Number: 001-02366 Rev. *D
Page 30 of 40
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