IBIS4-A-6600 Datasheet, PDF (27/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
Figure 20. Basic Frame and Line Timing
IBIS4-A-6600
CYII4SM6600AB
Pixel Output Timing
Using Two Analog Outputs
Figure 21. Pixel Output Timing using Two Analog Outputs
The pixel signal at the OUT1 (OUT2) output becomes valid
after 4 SYS_CLOCK cycles when the internal X_SYNC (= start
of PIXEL_VALID output) has appeared (see Figure 21.). The
PIXEL_VALID and EOL/EOF pulses can be delayed by the
user through the DELAY register.
T1 .................................. Row blanking time (see Table 17. )
T2 ..................................................... 4 SYS_CLOCK cycles.
Multiplexing to One Analog Output
The pixel signal at the OUT1 output becomes valid after 5
SYS_CLOCK cycles when the internal X_SYNC (= start of
PIXEL_VALID output) has appeared (see Figure 22.). The
PIXEL_VALID and EOL/EOF pulses can be delayed by the
user through the DELAY register.
T1 ............................................................. Row blanking time
T2 ...................................................... 5 SYS_CLOCK cycles.
Document Number: 001-02366 Rev. *D
Page 27 of 40
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