IBIS4-A-6600 Datasheet, PDF (1/40 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

ADVANCE
INFORMATION
IBIS4-A-6600
CYII4SM6600AB
6.6 MP CMOS Image Sensor
Features
Table 1. Key Performance Parameters
Parameter
Typical Value
Active Pixels
Pixel Size
Optical format
Active Imager Size
Shutter Type
Maximum Data
Rate/Master Clock
Frame rate
ADC resolution
Sensitivity (@ 650 nm)
Dynamic Range
Full Well Charge
Temporal Noise
Dark current
2210 (H) x 3002 (V)
3.5 µm x 3.5 µm
1 inch
7.74 mm x 10.51 mm
Electronic Rolling Shutter
40 MPS/40 MHz
5 fps (2210 x 3002)
89 fps (640 x 480)
ADC resolution
411 V.m2/W.s, 4.83 V/lux.s
59 dB
Full Well Charge
24 e-
3.37 mV/s
High Dynamic Range
Modes
Supply Voltage
Power consumption
Double Slope, Non Destructive
Read out (NDR).
Analog: 2.5V-3.3V, Digital: 2.5V,
I/O: 2.5V
190 mWatt
Table 1. Key Performance Parameters (continued)
Parameter
Operating temperature
Color Filter Array
Packaging
Typical Value
–30 °C to +65 °C
Mono, RGB Bayer Pattern
68-pins LCC
Description
The IBIS4-6600 is a solid -state CMOS image sensor that
integrates the functionality of complete analog image
acquisition, digitizer and digital signal processing system on a
single chip. The image sensor compromises a 6.6 MPixel
resolution with 2210x3002 active pixels. The image size is fully
programmable to user-defined windows of interest. The pixels
are on a 3.5-µm pitch. The sensor is available in a
Monochrome version or Bayer (RGB) patterned color filter
array.
User-programmable row and column start/stop positions allow
windowing down to 2x1 pixel window for digital zoom. Sub
sampling reduces resolution while maintaining the constant
field of view. The analog video output of the pixel array is
processed by an on-chip analog signal pipeline. Double
Sampling (DS) eliminates the fixed pattern noise. The
programmable gain and offset amplifier maps the signal swing
to the ADC input range. A 10-bit ADC converts the analog data
to a 10-bit digital word stream. The sensor uses a 3-wire
Serial-Parallel (SPI) interface. It operates with a single 2.5V
power supply and requires only one master clock for operation
up to 40 MHz. It is housed in a 68-pin ceramic LCC package.
This data sheet allows the user to develop a camera system
based on the described timing and interfacing.
Applications
• Machine vision
• Biometry
• Document scanning
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-02366 Rev. *D
Revised January 2, 2007
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