STC5428 Datasheet, PDF (7/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Pin Name
REF12_N
CLK1_P
CLK1_N
CLK2_P
CLK2_N
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK8K
CLK2K
SRCSW
CS
SCLK
SDI
CLKE
SDO
NC
STC5428
Synchronous Clock for SETS
DATASHEET
Table 1: Pin Description
Pin #
I/O
Description
29
I Differential reference input 12 negative (LVPECL/LVDS)
21
O Clock output CLK1 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₁
LVPECL or LVDS
22
O Clock output CLK1 negative, 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₁
LVPECL or LVDS
23
O Clock output CLK2 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₂
LVPECL or LVDS
24
O Clock output CLK2 negative. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₂
LVPECL or LVDS
56
O Clock output CLK3. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₃ or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz or proprietary composite signal from Synthesizer F. LVCMOS.
58
O Clock output CLK4. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₄ or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz or proprietary composite signal from Synthesizer F. LVCMOS.
59
O Clock output CLK5. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₅, or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz or proprietary composite signal from Synthesizer F. LVCMOS.
62
O Clock output CLK6. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₆ or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz, or proprietary composite signal from Synthesizer F. LVCMOS.
64
O Clock output CLK7. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₇ or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz, or proprietary composite signal from Synthesizer F. LVCMOS.
66
O Clock output CLK8. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₈ or Synthe-
sizer G_T4 (T4); 2kHz, 8kHz, or proprietary composite signal from Synthesizer F. LVCMOS.
18
O 8kHz frame pulse signal, 50% duty cycle or programmable pulse width (T0)
19
O 2kHz frame pulse signal, 50% duty cycle or programmable pulse width (T0)
13
I Hard-wired manual reference pre-selection
47
I SPI bus chip select
50
I ALE: Address latch enable for Multiplex bus interface
SCLK: SPI Bus interface clock
46
I SPI bus data input
45
I Clock edge selection for SPI
53
I/O SPI bus data output
3, 31, 52,
54, 65
No connection. Not bonded.
Page 7 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014