STC5428 Datasheet, PDF (47/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
HO flush:
0 = Flush the long term history. After flush, the value of the register Long Term Accu History is the short-term his
tory at the time of flushing
1 = Flush both long term history and the device holdover history. After flush, the value of the register Device Hold
over History will be the fractional frequency offset of the calibrated internal freerun clock.
PLL_Event_Out, 0x3E (R/W)
Address
0x3E
Bit7
Event7
Bit6
Event6
Bit5
Event5
Bit4
Event4
Event0: Reserved
Event1: Reserved
Event2: Reserved
Event3: Reserved
Event4: Reserved
Event5: Reserved
Event6: Reserved
Event7: Reserved
Events are cleared by writing “1” to the bit positions
Default value: 0
PLL_Event_In, 0x3F (R/W)
Bit3
Event3
Bit2
Event2
Bit1
Event1
Bit0
Event0
Address
0x3F
Bit7
Event7
Bit6
Event6
Bit5
Event5
Bit4
Event4
Bit3
Event3
Bit2
Event2
Bit1
Event1
Bit0
Event0
Writing 1 to trigger the event. If the event is acknowledged by the STC5428, event bit is cleared to be 0.
Event0: Relock
Sets PLL to relock the selected reference input. If the device operates in phase-align mode, PLL rese
lects the frame edge, relocks and frame phase align to the reference input. If the device operates in
non phase-align mode, PLL relocks to the reference input and restart phase rebuild process.
Event1: Reserved
Event2: Reserved
Event3: Reserved
Event4: Reserved
Event5: Reserved
Event6: Reserved
Event7: Reserved
Default value: 0
EX_SYNC_Edge_Config, 0x40 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x40
Not used
Edge Select
Page 47 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014