STC5428 Datasheet, PDF(25/66 Page) Connor-Winfield Corporation

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STC5428 Datasheet, PDF (25/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

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STC5428

Synchronous Clock for SETS

DATASHEET

HHA bit

This bit indicates the availability of the device hold-

over history or the user-specified history (1=available,

0=unavailable), depending on which of history is pro-

grammed at the register Control Mode. If the device

holdover history is programmed, The HHA bit is set to

â1â whenever the device holdover history is being

updated by the long-term history. The HHA bit stays

at â1â and the value of the device holdover history

freezes at the latest value if reference is switched,

LOS/LOL occurs, entering freerun/holdover mode, or

the long-term history is flushed alone by writing â0â to

the register Holdover Accu Flush. The HHA bit is

set to â0â (unavailable) when the device holdover his-

tory is flushed by writing â1â to the register Holdover

Accu Flush. If the user-specified history is pro-

grammed, the HHA bit is always set at â1â.

Briefly, when no reference input is selected or the

selected reference input is invalid during in automatic

reference selection mode, HHA bit at â1â implies the

STC5428 is entering holdover mode with a holdover

history; HHA bit at â0â implies the STC5428 is enter-

ing freerun mode instead of holdover mode.

Reference Inputs Details

The STC5428 accepts 12 external reference inputs.

The reference inputs may be selected to accept either

the auto-detect acceptable reference frequency which

can be automatically detected by STC5428 or manu-

ally acceptable reference frequency. Reference

inputs REF11 and REF12 are LVPECL/LVDS and the

remaining ten are LVCMOS. Signal polarity of REF11

and REF12 is reversible at the register Diff Ref

Polarity. All 12 reference inputs are monitored contin-

uously for frequency, activity and quality. Each timing

generator may select any of the reference inputs

when the device is in external timing mode. T4 may

accept T0âs output as its input via internal feedback

path.

Acceptable Frequency and Frequency Offset

Detection

The STC5428 can automatically detect the frequency

of the reference input when the user enable the auto-

detection function at the register Ref Index Selector

and Ref Acceptable Freq. The acceptable auto-

detect frequencies are: 8kHz, 64kHz, 1.544MHz,

2.048MHz, 19.44MHz, 38.88MHz, 77.76MHz,

6.48MHz, 8.192MHz, 16.384MHz, 25MHz, 50MHz or

125MHz. These frequencies can be automatic

detected continuously in the detector. Any carrier fre-

quency change willFbuendcetiteocnteadl Swpitheincif1imcas.tioEanch

input is also monitored for frequency offset between

input and the internal freerun clock. The frequency

offset is a key factor to determine qualification of the

reference inputs. See register Ref Index Selector

and Ref Info.

STC5428 provides another option which allows the

user to select the manually acceptable reference fre-

quency for all the reference inputs, at the integer mul-

tiple of 8kHz (Nx8kHz, N is integer from 1 to 32767).

Hence the manually acceptable reference frequency

range is integer multiple of 8kHz from 8kHz to

262.136MHz. When a manually acceptable reference

frequency is used, the user need to access the regis-

ter Ref Acceptable Freq to set the integer N for the

reference input which is selected at the register Ref

Index Selector. Each input is monitored for fre-

quency offset between input and the internal freerun

clock. The frequency offset is shown in the register

Ref Info when associate reference index is selected

at the register Ref Index Selector.

Activity Monitoring

Activity monitoring is also a continuous process which

is used to identify if the reference input is in normal. It

is accomplished with a leaky bucket accumulation

algorithm, as shown in Figure 2. The âleaky bucketâ

accumulator has a fill observation window that may

be set from 1 to 16ms, where any hit of signal abnor-

mality (or multiple hits) during the window increments

the bucket count by one. The leak observation win-

dow is 1 to 16 times the fill observation window. The

leaky bucket accumulator decrements by one for

each leak observation window that passes with no

signal abnormality. Both windows operate in a con-

secutive, non-overlapping manner. The bucket accu-

mulator has alarm assert and alarm de-assert

thresholds that can each be programmed from 1 to

64.

Page 25 of 66

Preliminary

Rev: 0.2

Date: April 3, 2014

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