STC5428 Datasheet, PDF (30/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
to this register to select master or slave mode.
Default selection is the hardware select using pin MC/
SL
In master/slave configuration, slave device synchro-
nizes and frame phase aligns with the master device,
using 100Hz loop bandwidth instead of the loop band-
width programmed at the register Loop Bandwidth.
In order to achieve master/slave frame phase align-
ment, two signals (one cross reference clock and one
frame reference clock) or one signal (contains both
cross reference and frame reference clock) is inter-
connected between the master and slave. The combi-
nation of cross reference and frame reference clock
has four options:
1. High frequency output of master device feeds into
REF7 of slave device as cross reference; Frame
pulse 8kHz or 2kHz output of master device
feeds into EX_SYNC of slave device as frame
reference.
2. Frame pulse 8kHz output of master device feeds
into EX_SYNC of slave device as cross reference
and frame reference.
3. Proprietary composite signal of master device
feeds into REF7 of slave device as cross refer-
ence and frame reference.
4. Proprietary composite signal of master device
feeds into EX_SYNC as cross reference clock
and frame reference.
To achieve 2kHz frame alignment, option 1, 3, or 4
should be selected. 8kHz on EX_SYNC pin cannot
produce 2kHz frame alignment. See the register
Slave Frame Align for cross reference clock and
frame reference clock selection details. If an error
occurs when sampled on the selected frame edge of
the cross reference, bit FEE of register PLL Status
will be asserted. Master’s frame pulse output CLK8K
replace the selected frame reference input as the
temporary frame reference. This error does not send
alarm of synchronization failure or loss of lock. User
can invoke a relock event to PLL by programming the
register PLL Event In. The frame edge is re-selected
as well.
User can select either falling edge or rising edge for
frame reference input EX_SYNC when the frame
reference input on pin EX_SYNC is not composite
signal. See the register EX SYNC Edge Config.
The proprietary composite signal contains not only
cross reference clock and the frame reference clock
of the master device but the information of the
selected reference of the master device. Having this
information, the slaFveunucntitioisnaalbSlepetociifdiecnatitfiyonthe
selected reference of the master device. Therefore, in
automatic reference selection mode, when the slave
device takes it over to be the new master device, it
can select the reference clock which previous master
device was locked to by setting bit Slave Inherit Mode
of the register Control Mode. However, if the new
master device operates in revertivity mode or has
different qualification results than previous master
device, it will select any preferred reference input.
In master/slave mode, for the latency delay on the
cross-couple path, it may be compensated up and
down 3.2s, in 0.1ns step. This will then minimize the
phase hits to the downstream devices resulting from
master/slave switches.
Multiple Master Configuration
In multiple master configuration, every unit works as
master and locks to the same reference input. Each
unit has consistent loop bandwidth settings. To
achieve frame phase alignment for all the masters’
outputs, each device has to choose same frame edge
on the selected reference input clock. The system
may provides every master a common extra frame
reference or simply choose a 8kHz reference input.
Frame reference clock and frame edge on each refer-
ence input is configured at register Master Frame
Align. If an error occurs when sampled on the
selected frame edge of the selected reference, bit
FEE of register PLL Status will be asserted and
frame pulse output CLK8K replaces the selected
frame reference input as the temporary frame refer-
ence. This error does not send alarm of synchroniza-
tion failure or loss of lock. User can invoke a re-lock
event to PLL by programming the register PLL Event
In. The frame edge is re-selected as well.
Multiple master configuration works only in frame
phase align mode. By writing to the Master Frame
Align register, user can set T0 timing generator to
frame phase align mode with the frame edge selec-
tion.
To meet the same synchronization and frame align-
ment requirements, each unit should keep the same
parameter setup, especially loop bandwidth. Multiple-
master mode demands a high quality external oscilla-
tor to obtain a precise frame phase alignment.
Page 30 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014