STC5428 Datasheet, PDF (45/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Bits 7 ~ 4
10
11
12
13
2s14, 15
Long Term
History -3dB
Bandwidth
1.2 mHz
0.62 mHz
0.31 mHz
0.15 mHz
Reserved
Bits 3 ~ 2
0
1
2
3
STC5428
Synchronous Clock for SETS
DATASHEET
History Settling Time
256s (with fast settling mode)
256s (with fast settling mode)
256s (with fast settling mode)
256s (with fast settling mode)
N/A
Short Term
History -3dB
Bandwidth
1.3 Hz
0.64 Hz
0.32 Hz
0.16 Hz
Bits 1 ~ 0
0
1
2
3
Default value: 0x57 (40mHz; 0.64Hz; 2ppm/sec)
Ref_Priority_Table, 0x36 (R/W)
Ramp control
No Control
1.0 ppm/sec
1.5 ppm/sec
2.0 ppm/sec
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
0x36
0x37
0x38
0x39
0x3A
0x3B
Ref 2 Priority
Ref 4 Priority
Ref 6 Priority
Ref 8 Priority
Ref 10 Priority
Ref 12 Priority
Ref 1 Priority
Ref 3 Priority
Ref 5 Priority
Ref 7 Priority
Ref 9 Priority
Ref 11 Priority
Reference priority for automatic reference selector. Lower values have higher priority:
Default value: 0
PLL_Status, 0x3C (R)
Bits 7~4/Bits 3~0
0
1 ~ 15
Reference Priority
Revoke from auto reference elector
Value 1 ~ 15
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
0x3C
HHA
DHT
FEE
SAP
OOP
LOL
LOS
Bit0
Bit0
SYNC
Page 45 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014