STC5428 Datasheet, PDF (31/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
Event Interrupts
The STC5428 events shown following below are
interrupt events might occurred.
- Qualification status of the reference inputs change
- Activity status of the cross reference inputs change
- Selected reference of timing generator T0 changes
in automatic reference selection
- Selected reference of timing generator T4 changes
in automatic reference selection
- PLL status of timing generator T0 changes
- PLL status of timing generator T4 changes
- Out-Event of timing generator T0 asserts
- Out-Event of timing generator T4 asserts
The interrupt events can be read from Interrupt Sta-
tus register. Each bit indicates one events. The asso-
ciate bit of the Interrupt Status will not be changed
automatically when the event is cleared. Therefore,
the user need write ‘1’ to the associate bit to erase
the event.
bytes firmware configuration data to the register
Field Upgrade DFautnacotnieonbaytleSapt eactiimfiecatotioconm-
plete data loading. User can read the same regis-
ter for the written byte. But regardless of how
many times the user read, only the last written
byte will be read from the register.
4. Read the register Field Upgrade Count for how
many bytes of configuration data has been
loaded. Bit Load_Compelet of the register Field
Upgrade Status will indicate whether the 7600
bytes loading is complete and meanwhile bit
CHECKSUM will indicate the loading is failed or
succeed. See register description of Field
Upgrade Status for details.
The STC5428 has a pin EVENT_ INTR (pin 8) for
indicating the event interrupt occurrence. The pin
may be wired to user’s micro-controller. User can pro-
gram the Interrupt Mask register to decide which of
interrupt events will send an alarm to the micro-con-
troller by asserting the EVENT_INTR pin. User can
program at the Interrupt Configuration register to
specify the logic level (active high or low) of the pin
EVENT_INTR when it’s trigged by the interrupt event.
User may also program the Interrupt Configuration
register to define pin states as tri-state or logic inac-
tive when no interrupt event occurs.
Field Upgradability
The STC5428 supports field upgradability which
allows the user to load size of 7600 byte firmware
configuration data (provided as per request) via bus
interface. Field upgrade can only be performed at
least 3ms after reset.
1. User may read Bit READY of the register Field
Upgrade Status to check if field upgrade is ready
to start.
2. To begin the field upgrade, write to register Field
Upgrade Start three times consecutively, with no
intervening read/writes from/to other registers,
see the register Field Upgrade Start for details.
3. Once the field upgrade process begins, the
STC5428 is hold for data loading. Write 7600
Page 31 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014