STC5428 Datasheet, PDF (50/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
Default value: 0
Master_Slave_Selection_Mode, 0x48 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x48
Not Used
Master_Slave_Selection_Mode
Determine which of ways to select T0 master/slave mode:
0 = selects T0 master/slave mode using pin MC/SL (hardware select).
The states of pin MC/SL can be read from the register T0_MS_Sts.
1 = selects T0 master/slave mode using the register T0_MS_Sts (register select).
Write to the register T0_MS_Sts to select master or slave mode.
Default value: 0
Synth_Index_Select, 0x4A (R/W)
Address
Bit7
0x4A
Bit6
Bit5
Not Used
Bit4
Bit3
Bit2
Bit1
Bit0
Synthesizer index selection for synthesizer frequency and
phase skew adjustment
Determines which synthesizer is selected for setting frequency value at the register Synth_Freq_Value and
adjusting phase skew at the register Synth_Skew_Adj.
CLK1~CLK8 can be derived from synthesizer G₁~G₈ through T0 path, respectively, in which CLK3~CLK8 can
also be derived from synthesizer F through T0 path or synthesizer G_T4 through T4 path.
Default value: 0
Field Value
0
1
2
3
4
5
6
7
8
9
Synthesizer
Synthesizer F
Synthesizer G₁
Synthesizer G₂
Synthesizer G₃
Synthesizer G₄
Synthesizer G₅
Synthesizer G₆
Synthesizer G₇
Synthesizer G₈
Synthesizer G_T4
Associated CLK Output
CLK8K, CLK2K, CLK3~CLK8
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK3~CLK8
Page 50 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014