STC5428 Datasheet, PDF (53/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

CLK3_Sel, 0x53 (R/W)
STC5428
Synchronous Clock for SETS
DATASHEET
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x53
Not used
CLK3 Synthesizer Select
Selects the clock output CLK3 derived from synthesizer G₃ (T0), synthesizer F or synthesizer G_T4 (T4). Com-
posite signal, Frame8K, and Frame2K are all produced at synthesizer F. When synthesizer F is selected, sets
bit1~bit0 of the register Frame_Mux to select frame pulse clock from composite signal, Frame8K, or Frame2K.
Signal level of CLK3 is LVCMOS.
Register
Frame_Mux
(Bit1~Bit0)
X
X
0
1
2
3
X
Register
CLK3_Sel
(Bit1~Bit0)
0
1
2
2
2
2
3
CLK3 Synthesizer Select
Put CLK3 in tri-state mode
Synthesizer G₃ (T0)
Synthesizer F composite signal (T0)
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK3 tie to ground
Synthesizer G_T4 (T4)
Default value: 0
CLK4_Sel, 0x54 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x54
Not used
CLK4 Synthesizer Select
Selects the clock output CLK4 derived from synthesizer G₄ (T0), synthesizer F or synthesizer G_T4 (T4). Com-
posite signal, Frame8K, and Frame2K are all produced at synthesizer F. When synthesizer F is selected, sets
bit3~bit2 of the register Frame_Mux to select frame pulse clock from composite signal, Frame8K, or Frame2K.
Signal level of CLK4 is LVCMOS.
Default value: 0
Register
Frame_Mux
(Bit3~Bit2)
X
X
0
1
2
3
X
Register
CLK4_Sel
(Bit1~Bit0)
0
1
2
2
2
2
3
CLK4 Synthesizer Select
Put CLK4 in tri-state mode
Synthesizer G₄ (T0)
Synthesizer F composite signal (T0)
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK4 tie to ground
Synthesizer G_T4 (T4)
Page 53 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014