STC5428 Datasheet, PDF (18/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
General Description
Application
The STC5428 is a single chip solution for the syn-
chronous clock in SDH (SETS), SONET, and Syn-
chronous Ethernet network elements. The device is
fully compliant with ITU-T G.813 (option1 and
option2), G.8262 EEC (option1 and option2), Telcor-
dia GR1244, and GR253 (Stratum3/4E/4/SMC). Its
highly integrated design implements all necessary
reference selection, monitoring, filtering, synthesis,
and control functions. An external oscillator (e.g., high
precision OCXO or TCXO) completes a system level
solution (see Functional Block Diagram, Figure 1).
The STC5428 has four programmable frequency
options of external oscillator. The STC5428 supports
master/slave and multiple-master operations for
redundant application.
Overview
The STC5428 accepts 12 reference inputs and gen-
erates 10 synchronized clock outputs, including 2
frame pulse clock outputs CLK8K and CLK2K at 8kHz
and 2kHz. Two independent PLL-based timing gener-
ators, T0 and T4, provide the essential functions for
Synchronous Equipment Timing Sources (SETS). T0
controls synthesizers G₁~G₈, and synthesizer F. T4
controls synthesizer G_T4. Clock outputs CLK1~CLK8
can be derived from synthesizer G₁~G₈, respectively.
CLK3~CLK8 can also be derived from synthesizer F
through T0 path or synthesizer G_T4 through T4 path.
Frame pulse clock outputs are derived from synthe-
sizer F. The STC5428 incorporates a microprocessor
interface, which can be configured for all common
microprocessor interface types.
activity and quality monitored. The reference inputs
may be selected toFuancccetpiot neaithleSr ptehecifaiuctao-tdioetnect
acceptable reference frequency which can be auto-
matically detected by STC5428 or manually accept-
able reference frequency. The activity monitoring is
implemented with a programmable leaky bucket algo-
rithm.
A reference is designated as “qualified” if it is active
and its fractional frequency offset is within the pro-
grammed range for a programmed soaking time. An
auto reference elector elects the most appropriate
one from the reference inputs according to the
revertive status, and each reference’s priority and
qualification. Revertive status determines whether a
higher priority qualified reference should preempt a
qualified current auto-elected reference. If none of the
references input is qualified, holdover or freerun
mode will be elected depending on the availability of
the holdover history.
Reference selection may be automatic, manual, or
hard-wired manual. In automatic reference selection
mode, the most appropriate one elected from the auto
reference elector will be the selected reference input.
In manual reference selection mode, user may spec-
ify any of the reference inputs as the selected refer-
ence input for external timing or holdover/freerun for
self-timing. In hard-wired manual mode, user can fast
switch using control pin SRCSW between two pre-
programmed reference inputs. The reference input
elected from the auto reference elector will not affect
the selected reference input in manual or hard-wired
manual mode.
In manual reference selection mode, the timing gen-
erator T4 may accept T0’s synchronized output as its
input.
Chip Master Clock
The STC5428 operates with an external oscillator
(e.g., OCXO or TCXO) as its master clock. The
device supports four different frequencies of master
clock: 10MHz, 12.8MHz, 19.2MHz, and 20MHz. Initial
default accepted frequency is 12.8MHz.
Reference Inputs
The STC5428 accepts 12 reference inputs. REF11
and REF12 are LVPECL/LVDS, remaining 10 are
LVCMOS. The 12 reference inputs are continuously
Timing Generators and Operation
Modes
The STC5428 includes two independent timing gen-
erators, T0 and T4, to provide the essential functions
for SETS. Each timing generator can individually
operate in Freerun, Synchronized, Pseudo-Hold-
over and Holdover mode. A timing generator is in
either external-timing mode or self-timing mode. In
external timing mode, PLL of the timing generator
phase locks to the selected external reference input.
In self-timing mode, the PLL simply tunes the clock
Page 18 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014