STC5428 Datasheet, PDF (33/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
CS
t_CS
t_CSHLD
t_CSMIN
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCLK
t_Ds
t_Dh
t_CL
t_CH
SDI
0 ^{A0 A1 A2 A3 A4 A5 A6} D0 ^{D1 D2 D3} D4 ^{D5 D6 D7}
LSB
MSB LSB
MSB
Figure 10:SPI Bus Timing, Write access
Table 11: SPI Bus Timing
Symbol
t_CS
t_CH
t_CL
t_Ds
t_Dh
t_DRDY
t_DHLD
t_CSHLD
t_CSTRI
t_CSMIN
Description
CS low to SCLK high
SCLK high time
SCLK low time
Data setup time
Data hold time
Data ready
Data hold
CS hold
CS off to data tri-state
Minimum delay between successive accesses
Min
10
50
50
10
10
3
30
1 / freq_MCLK ^*
Max
7
5
Note*: freq_MCLK could be at 10MHz, 12.8MHz, 19.2MHz, or 20MHz. See Chip Master Clock for details.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 33 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014