STC5428 Datasheet, PDF (55/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

CLK7_Sel, 0x57 (R/W)
STC5428
Synchronous Clock for SETS
DATASHEET
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x57
Not used
CLK7 Synthesizer Select
Selects the clock output CLK7 derived from synthesizer G₇ (T0), synthesizer F or synthesizer G_T4 (T4). Com-
posite signal, Frame8K, and Frame2K are all produced at synthesizer F. When synthesizer F is selected, sets
bit9~bit8 of the register Frame_Mux to select frame pulse clock from composite signal, Frame8K, or Frame2K.
Signal level of CLK7 is LVCMOS.
Register
Frame_Mux
(Bit9~Bit8)
X
X
0
1
2
3
X
Register
CLK7_Sel
(Bit1~Bit0)
0
1
2
2
2
2
3
CLK7 Synthesizer Select
Put CLK7 in tri-state mode
Synthesizer G₄ (T0)
Synthesizer F composite signal (T0)
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK7 tie to ground
Synthesizer G_T4 (T4)
Default value: 0
CLK8_Sel, 0x58 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x58
Not used
CLK8 Synthesizer Select
Selects the clock output CLK8 derived from synthesizer G₈ (T0), synthesizer F or synthesizer G_T4 (T4). Com-
posite signal, Frame8K, and Frame2K are all produced at synthesizer F. When synthesizer F is selected, sets
bit11~bit10 of the register Frame_Mux to select frame pulse clock from composite signal, Frame8K, or
Frame2K. Signal level of CLK8 is LVCMOS.
Default value: 0
Register
Frame_Mux
(Bit11~Bit10)
X
X
0
1
2
3
X
Register
CLK8_Sel
(Bit1~Bit0)
0
1
2
2
2
2
3
CLK8 Synthesizer Select
Put CLK8 in tri-state mode
Synthesizer G₄ (T0)
Synthesizer F composite signal (T0)
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK8 tie to ground
Synthesizer G_T4 (T4)
Page 55 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014