STC5428 Datasheet, PDF (22/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
tory. This history was accumulated by a built-in pro-
grammable short-term history accumulator
consecutively, which presents the latest updated frac-
tional frequency offset of the synchronous clock out-
put of each timing generator. The user can read the
short-term history from register Short Term Accu
History.
Holdover Mode
Holdover mode is typically used when current
selected reference lost and no other valid reference
input is available to replace. In holdover mode, an
average frequency offset between the clock output
and MCLK is used for maintaining the clock output as
closely as possible to previous output when the
selected reference input was valid. This average fre-
quency offset is either device holdover history or user
specified holdover history which can be selected at
the register Control Mode. See section of Histories
of Fractional Frequency Offset for holdover history
details.
PLL Event In
The STC5428 provides direct communication with the
PLL’s timing generator by writing to the register PLL
Event In. Following events can be triggered:
- Relock. PLL starts a relock process if this event is trig-
gered. In frame phase align mode, PLL relocks to the ref-
erence input and the frame edge is re-selected as well.
In phase arbitrary mode, PLL relocks to the reference
input and restart the phase rebuild process.
Frequency and Phase Transients
Severe frequency and phase transients of the clock
output will cause lost of lock or buffer overflow/under-
flow on downstream circuit. By providing programma-
ble maximum slew rate and phase rebuild function,
both frequency and phase transient of the STC5428’s
clock output is controlled to minimize the impact on
downstream circuits.
Frequency Transients
The STC5428 smoothly control the frequency tran-
sient on the clock output. During reference input
switching or operation mode switching (etc., switch to
freerun or holdover mode), if the clock output prior to
switching has different frequency offset than the
desired clock output, it smoothly approaches to
desired frequency offset with a maximum accelera-
tion/deceleration rate by writing to the register History
Ramp. The maximum slew rate can be programmed
as 1.0, 1.5, 2.0 ppmF/suecnocntdi.oWniathl Sa plimeciteifdicaacctieolenra-
tion/deceleration, the pull-in process may last longer.
However, it will minimize the frequency transient
impact to the downstream clock and ensure meeting
components frequency impact tolerance.
Phase Transients
The STC5428 minimize the variation of the phase
transient on the clock output when a phase hit occurs
on the selected reference input. The overshoot in the
clock output’s phase transient response will be a
small amount under 2%.
During reference input switching or recovering from
LOS/LOL condition, the phase transient is also
occurred on the clock output. The STC5428 can mini-
mize it with a phase rebuild function. In synchronized
mode, the phase relationship between the reference
input and the clock output can be programmed to
phase arbitrary or frame phase align at the register
Master Frame Align. If phase arbitrary is selected, a
phase rebuild function is performed before locking to
the new/recovered reference input. Hit-less switching
is achieved with this function and the phase hit to
downstream circuits is eliminated. If frame phase
align is selected, the clock output is in frame phase
alignment with the reference input. Only T0 timing
generator supports frame phase alignment.
Histories of Fractional Frequency
Offset
The STC5428 has two timing generators, T0 and T4.
Each of timing generators has two history data accu-
mulators which internally implemented with two 3rd
order low pass filters. One is for short-term history
build up and the other is for long-term history build up.
Both accumulators will always perform accumulation
of the average frequency offset between the clock
output and MCLK. A developed long-term history will
begin and continuously update as Device Holdover
History which may be used to determine the fractional
frequency offset of clock output when the STC5428
enters the holdover mode. In addition, the STC5428
allows user to program a user specified history to
maintain the clock output in holdover mode. The fol-
lowing description has more details.
Page 22 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014