STC5428 Datasheet, PDF (54/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

CLK5_Sel, 0x55 (R/W)
STC5428
Synchronous Clock for SETS
DATASHEET
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x55
Not used
CLK5 Synthesizer Select
Selects the clock output CLK5 derived from synthesizer G₅ (T0), synthesizer F or synthesizer G_T4 (T4). Com-
posite signal, Frame8K, and Frame2K are all produced at synthesizer F. When synthesizer F is selected, sets
bit5~bit4 of the register Frame_Mux to select frame pulse clock from composite signal, Frame8K, or Frame2K.
Signal level of CLK5 is LVCMOS.
Register
Frame_Mux
(Bit5~Bit4)
X
X
0
1
2
3
X
Default value: 0
CLK6_Sel, 0x56 (R/W)
Register
CLK5_Sel
(Bit1~Bit0)
0
1
2
2
2
2
3
CLK5 Synthesizer Select
Put CLK5 in tri-state mode
Synthesizer G₄ (T0)
Synthesizer F composite signal (T0)
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK5 tie to ground
Synthesizer G_T4 (T4)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x56
Not used
CLK6 Synthesizer Select
Selects the clock output CLK6 derived from synthesizer G₆ (T0), synthesizer F or synthesizer G_T4 (T4). Com-
posite signal, Frame8K, and Frame2K are all produced at synthesizer F. When synthesizer F is selected, sets
bit7~bit6 of the register Frame_Mux to select frame pulse clock from composite signal, Frame8K, or Frame2K.
Signal level of CLK6 is LVCMOS.
Default value: 0
Register
Frame_Mux
(Bit7~Bit6)
X
X
0
1
2
3
X
Register
CLK6_Sel
(Bit1~Bit0)
0
1
2
2
2
2
3
CLK6 Synthesizer Select
Put CLK6 in tri-state mode
Synthesizer G₄ (T0)
Synthesizer F composite signal (T0)
Synthesizer F Frame8K
Synthesizer F Frame2K
CLK6 tie to ground
Synthesizer G_T4 (T4)
Page 54 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014