STC5428 Datasheet, PDF (23/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
Short-Term History
Short-term history is an average frequency offset
between the clock output and MCLK which is filtered
internally using a 3rd order low-pass filter. The -3dB
filter response point can be programmed for 0.16Hz,
0.32Hz, 0.64Hz, and 1.3Hz by writing to the register
History Ramp. Short-term history can be read from
the register Short Term Accu History. Typically,
short-term history is used by clock synthesizer in two
conditions: First, it is used in pseudo holdover mode;
second, it is used if loss of signal (LOS) occurs when
the STC5428 operates in manual reference selection
mode. In addition, short-term history is provided to
perform failure diagnostics and evaluations.
Long-Term History
Long-term history is also an average frequency offset
between the clock output and MCLK which is filtered
internally using a 3rd order low-pass filter. The -3dB
filter response point can be programmed from
0.15mHz to 1.3Hz by writing to the register History
Ramp. Long-term history value can be read from the
register Long Term Accu History.
User can flush the long-term history by writing “0” or
“1” to the register Holdover Accu Flush. Notice: writ-
ing “1” to this register will not only flush the long-term
history but also the device holdover history. See sec-
tion Device Holdover History for details.
Device Holdover History
The device holdover history, acquired from the long-
term history, is used when the STC5428 enters the
holdover mode with the holdover history usage pro-
grammed as Device Holdover History at the register
Control Mode. After the clock output is synchronized
to the selected reference input for a period of History
Settling Time, the device holdover history will begin
and be continuously updated at the register Device
Holdover History by the long-term history. The
length of History Settling Time varies with a choice of
the long-term history -3dB bandwidth. For bandwidth
of 1.3Hz down to 9.9mHz, the History Settling Time is
2s to 256s as shown in Table 10. This table is also
shown in the description of the register History
Ramp. For extreme narrow bandwidth of 4.9mHz
down to 0.15mHz, the History Settling Time is only
256s as a result of an internal fast settling mode tem-
porarily applied to speed up the time.
Once the device holdover history begin and be con-
tinuously updated byFuthneclotinogn-taerlmSphiestcoirfyi,ctahteioDnHT
bit (indicates whether the device holdover history is
being updated by the long-term history) value of the
register PLL Status is set and remains at “1”. In the
meantime, the HHA bit (indicates holdover history
availability) in the same register is set to “1” indicating
that the device holdover history is currently available
if the holdover history usage programmed as Device
Holdover History at the register Control Mode.
Updating will stop if reference is switched, LOS/LOL
occurs, or entering freerun/holdover mode. In addi-
tion, updating will stop if the long-term history is
flushed alone by writing “0” to the register Holdover
Accu Flush. The device holdover history freezes at
the latest history value when updating stops. The
updating will then resume if the device reenters the
synchronized mode for another period of History Set-
tling Time. Accordingly, the DHT bit reverts to “0”
when updating stops and set back to “1” when updat-
ing resume. The HHA bit stays at “1” when updating
stops indicating the device holdover history is still
available (the latest history value when updating
stops) if the holdover history usage programmed as
Device Holdover History at the register Control
Mode. The device holdover history can be read from
the register Device Holdover History.
User can flush the device holdover history by writing
“1” to the register Holdover Accu Flush. Notice: this
writing will not only flush the device holdover history
but also the long-term history. Upon writing “1” to
flush both history, the value at the register Device
Holdover History will be the fractional frequency off-
set of the calibrated internal freerun clock and the
HHA bit is set to “0” reflects the device holdover his-
tory is currently unavailable if the holdover history
usage programmed as Device Holdover History at the
register Control Mode. Also the DHT bit is set to “0”
reflects the device holdover history stops being
updated by the long-term history because of the long-
term history has been flushed.
Table 10: History Settling Time
Long Term History
-3dB Bandwidth
1.3Hz
0.64Hz
History Settling Time
2s
4s
Page 23 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014