STC5428 Datasheet, PDF (24/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
Table 10: History Settling Time
0.32Hz
0.16Hz
79mHz
40mHz
20mHz
9.9mHz
4.9mHz
8s
16s
32s
64s
128s
256s
256s (with fast settling
mode)
2.5mHz
256s (with fast settling
mode)
1.2mHz
0.62mHz
0.31mHz
0.15mHz
256s (with fast settling
mode)
256s (with fast settling
mode)
256s (with fast settling
mode)
256s (with fast settling
mode)
User-Specified History
User-specified history is the holdover history written
to the register User Specified History and used
when the STC5428 enters the holdover mode with
the holdover history usage programmed as user-
specified history at the register Control Mode. Its
value can be read back from the same register. The
HHA bit of the register PLL Status is set at “1” as
long as usage of the user-specified history is selected
at the register Control Mode.
In external-timing mode, this bit indicates the loss of
signal on the selecteFdurnefcetreionncea.lTShpisebcitifwicillaatlisoonbe
asserted in self-timing mode (freerun, pseudo hold-
over and holdover).
LOL bit
In external-timing mode, the bit will be set if the PLL
fails to achieve or maintain lock to the selected refer-
ence. This bit will also be asserted in self-timing
mode (freerun, pseudo holdover and holdover). It is
also not complementary to the SYNC bit. Both bits will
not be asserted when the PLL is in the pull-in pro-
cess. The pull-in process usually occur when switch
to a new selected reference or recover from the LOS/
LOL.
OOP bit
This bit indicates that the selected reference is out of
the pull-in range. This is meaningful only if in exter-
nal-timing mode. This bit will not be asserted in self-
timing mode. The frequency offset is relative to the
digitally calibrated freerun clock.
SAP bit
This bit when set indicates that the PLL’s output
clocks have stopped following the selected reference
because the frequency offset of the selected refer-
ence is out of pull-in range (OOP). User can write to
the Control Mode register to program whether the
PLL shall follow the selected reference outside of the
specified pull-in range or just stay within the pull-in
range boundary.
FEE bit
This bit indicates whether an error occurs in the frame
edge detection process in slave mode or master
phase align mode. For timing generator T0 only.
Phase-Locked Loop Status Details
The register PLL Status contains the detailed status
of the PLLs, including the signal activity of the
selected reference, the synchronization status, and
the availability of the holdover histories.
SYNC bit
In external-timing mode, this bit indicates the
achievement of synchronization. This bit will not be
asserted in self-timing mode.
LOS bit
DHT bit
This bit indicates whether the device holdover history
is being updated by the long-term history (0=not
updating, 1= updating). The device holdover history
will begin and be continuously updated by the long-
term history after the clock output is synchronized to
the selected reference input for a period of History
Settling Time (See section Device Holdover History
for details). Updating will stop if reference is switched,
LOS/LOL occurs, or entering freerun/holdover mode.
Additionally, updating will stop if the long-term history
is flushed by writing “0” or “1” to the register Holdover
Accu Flush.
Page 24 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014