STC5428 Datasheet, PDF (28/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
wired Manual Reference Selection is for T0 only.
Clock Outputs Details
The STC5428 generates 2 synchronized differential
(LVPECL or LVDS) clock outputs: CLK1 and CLK2; 6
LVCMOS clock outputs: CLK3~CLK8; frame pulse
clock outputs CLK8K and CLK2K. Figure 5, Figure 6,
and Figure 7 respectively shows the clock output sec-
tion for CLK1/CLK2, CLK8K/CLK2K, and
CLK3~CLK8. Each output has individual clock output
section consist of a synthesizer and a clock genera-
tor. Clock generator of CLK1 or CLK2 has a LVPECL/
LVDS driver to produce differential output. Each gen-
erator of CLK3~CLK8 includes two muxes and a LVC-
MOS signal driver. Generator of frame output CLK8K
and CLK2K consist of a LVCMOS driver.
Clock Synthesizers
The STC5428 has 10 clock synthesizers, which of 9
is disciplined by the timing generator T0: synthesizer
G1~G8 and one frame pulse clock synthesizer F; T4
disciplines a clock synthesizer G_T4. Clock synthesiz-
ers G₁~G₈ produce frequencies from 1MHz to
156.25MHz, in 1kHz steps. Phase skew of these syn-
thesizers are all programmable individually up and
down 50ns at the register Synth Index Select and
Synth Skew Adj. CLK1 and CLK2 are derived from
synthesizer G₁ and G₂. CLK3 ~ CLK8 can be derived
from synthesizer G₃~G₈, also can be derived from
synthesizer F or from synthesizer G_T4 respectively.
Synthesizer F produces frame pulse clock Frame8K,
Frame2K, and a proprietary composite signal. Syn-
thesizer F has two independent duty cycle controller
for Frame8K and Frame2K which can program pulse
width at the register Frame8K Sel and Frame2K Sel.
Proprietary composite signal is a 3.3V LVCMOS data
signal carries 8kHz clock, 2kHz frame, and the
selected reference information.
Clock Generators
Clock generator of CLK1 or CLK2 consist of a
LVPECL/LVDS signal driver. The signal level of clock
outputs CLK1 and CLK2 can be programmed to
either LVPECL or LVDS at the register CLK1/2 Sig-
nal Level. Clock generators of CLK3~CLK8 consist
of a Frame Mux, CLK Sel Mux and a LVCMOS driver.
CLK Sel Mux determines which synthesizer is
selected for generator to output clock. When synthe-
sizer F is selected, Frame Mux selects one of frame
clocks (Frame8K, Frame2K, and proprietary compos-
ite signal) derived from synthesizer F and forward it to
CLK Sel Mux foFr unfrcamtioe nasilgSnaplecsieflieccatitoinonof
CLK3~CLK8 individually. Frame Mux is set at the reg-
ister Frame Mux and the CLK(3~8) Sel Mux is set at
the registers CLK(3~8) Sel for CLK3 ~ CLK8 individu-
ally. Signal level of CLK3~CLK8 is driven from LVC-
MOS driver in clock generator.
The clock generator of CLK8K and CLK2K contains a
LVCMOS driver. Clock outputs CLK8K and CLK2K
output Frame8K and Frame2K clock pulse clock. The
duty cycle is programmable at the register Frame8K
Sel and Frame2K Sel.
Synthesizer G₁
1MHz ~ 156.25MHz
CLK1 Generator
LVPECL
/LVDS
DRIVER
CLK1
Synthesizer G₂
1MHz ~ 156.25MHz
CLK2 Generator
LVPECL
/LVDS
DRIVER
CLK2
Figure 5:Output Clocks CLK1 and CLK2
Clock Output Phase Alignment
Any of clock outputs (except those derived from syn-
thesizer G_T4) which has frequency at the integer mul-
tiple of 8kHz is in phase alignment with the frame
pulse output CLK8K if none of synthesizer skew is
programmed.
Synthesizer Skew Programming
The STC5428 allows user to program the phase skew
of each clock synthesizer, up and down 50ns in
roughly 0.024ns steps. Since each of clock outputs is
dedicate derived from its synthesizer respectively,
adjust phase skew of the synthesizer will provide the
associated clock output a phase skew adjustment.
Phase skew of the 10 synthesizers may be pro-
grammed at the register Synth Index Select and
Synth Skew Adj.
Page 28 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014