STC5428 Datasheet, PDF (1/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
Description
Features
Functional Specification
The RoHS compliant STC5428 is a single chip clock syn-
chronization solution for applications in SDH/SETS,
SONET, and Synchronous Ethernet network elements. The
device is fully compliant with ITU-T G.813 option 1 and 2,
G.8262 EEC option 1 and 2, Telcordia GR1244 and GR253.
The STC5428 accepts 12 clock reference inputs and gener-
ates 10 synchronized clock outputs: CLK1~CLK8, frame
pulse clock CLK8K at 8kHz, and frame pulse clock CLK2K
at 2kHz. CLK1~CLK8 may be programmed for wide variety
of frequencies from 1MHz up to 156.25MHz, in 1kHz steps.
Reference inputs are individually monitored for activity and
quality. Reference selection may be automatic, manual, and
hard-wired manual.
Two independent timing generators, T0 and T4, may oper-
ate in the Freerun, Synchronized, Pseudo Holdover, and
Holdover mode. Each timing generator includes a DSP-
based PLL. Synchronized mode is an external timing mode
while freerun and holdover are self-timing modes. T0 sup-
ports master/slave and multiple master operation for redun-
dant design. T4 supports master operation only. DSP-based
PLL technology removes any external component except
the oscillator. It provides excellent performance and reliabil-
ity to STC5428.
The STC5428 is clocked by an external oscillator (TCXO or
OCXO). Using a well-chosen external oscillator ensures the
STC5428 meet the required specifications and standards.
- Complies with ITU-T G.813 Opt1/Opt2, G.8262 EEC
Opt1/Opt2, Telcordia GR1244 and GR253 (Stratum3/4E/
4/SMC)
- Two timing generators T0 and T4; T4 may lock to T0’s
synchronized output
- Supports Master/Slave and Multiple-Master redundant
application (T0 timing generator only)
- Provides programmable compensation for phase delay
between master and slave unit, in 0.1ns steps
- Accepts external oscillator at frequency of 10MHz,
12.8MHz, 19.2MHz,or 20MHz with programming
- Accepts 12 clock reference inputs
- Supports frequency auto detection or manually accept-
able frequency for reference inputs. Each of them is
monitored for activity and quality
- Automatic/manual/hard-wired manual reference select
- Outputs 10 synchronized clock outputs, including 2
frame pulse clocks CLK8K and CLK2K
- 10 clock synthesizers generate frequencies
- Programmable phase skew at synthesizer level
- Phase-align or hit-less reference locking/switching
- Programmable loop bandwidth, from 0.1Hz to 100Hz
- Supports SPI bus interface
- Single 3.3V operation
- IEEE 1149.1 JTAG boundary scan
- 68-pin QFN package
SRCSW
Master_Slave
EX_SYNC
Ref Clk
12
10 LVCMOS
+
2 LVPECL/LVDS
TCXO
OCXO
2
T0 Timing
Generator
Synthesizer G₁
Synthesizer G₂
Synth
F
Frame8K
Frame2K
Composite
Synthesizer G₃
Synthesizer G₄
Ref
Monitor
Synthesizer G₅
Synthesizer G₆
Synthesizer G₇
T4 Timing
Generator
Synthesizer G₈
Synthesizer G_T4
SPI Interface
Figure 1:Functional Block Diagram
CLK1, LVPECL/LVDS
CLK2, LVPECL/LVDS
CLK8K
CLK2K
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
Page 1 of 66
Preliminary
Tm126 Rev: 0.2
Date: April 3, 2014
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice. Not intended for life support applications