STC5428 Datasheet, PDF (57/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
Default value: 0
Frame_Mux, 0x5D (R/W)
Address
0x5D
0x5E
Bit7
Bit6
Bit5
Bit4
Frame mux of
CLK6 selection
Not used
Frame mux of
CLK5 selection
Bit3
Bit2
Frame mux of
CLK4 selection
Frame mux of
CLK8 selection
Bit1
Bit0
Frame mux of
CLK3 selection
Frame mux of
CLK7 selection
Select one of frame signals (Frame8K, Frame2K, and composite signal) derived from synthesizer F and for-
ward it to output selection of CLK3~CLK8 individually. Output selection of CLK3~CLK8 is programmed at the
registers CLK(3~8)_Sel.
Bit1~Bit0
Bit3~Bit2
Bit5~Bit4
Bit7~Bit6
Bit9~Bit8
Bit11~Bit10
0
1
2
3
Default value: 0
Diff_REF_Polarity, 0x5F (R/W)
Frame signal select
Proprietary composite signal
Frame8K
Frame2K
Ground
Address
Bit7
Bit6
Bit5
Bit4
Bit3
0x5F
Not used
Bit2
Bit1
Bit0
REF12 Polarity
REF11 Polarity
Reverse polarity of positive and negative for differential reference input REF11_P/REF11_N and REF12_P/
REF12_N.
REF11/REF12 Polarity:
1 = Normal polarity
0 = Reverse polarity of P and N. Use falling edge of P instead of rising edge
Default value: 3
Field_Upgrade_Status, 0x70 (R)
Address
Bit7
0x70
Bit6
Bit5
Bit4
Not used
Bit3
Bit2
Load_Complete
Checksum
Checks whether the 7600 bytes firmware configuration data is loaded successfully.
0 = Fail, 1 = Success
Bit1
READY
Bit0
Checksum
Page 57 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014