STC5428 Datasheet, PDF (19/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5428
Synchronous Clock for SETS
DATASHEET
synthesizers to a given fractional frequency offset.
Synchronized mode is in external timing. PLL’s loop
bandwidth may be programmed individually to vary
the timing generator’s filtering function. Conversely,
freerun, pseudo-holdover and holdover modes are all
in self-timing. When selected reference input and pre-
vious holdover history are unavailable, such as in
system’s initialization stage, freerun mode may be
entered or used. When selected reference input is
unavailable but a long-term holdover history accumu-
lated in previous synchronized mode is available,
holdover mode may be entered or used. STC5428
may enter pseudo-holdover using short-term fre-
quency history. In STC5428, the freerun clock is
derived from the MCLK (external oscillator) and digi-
tally calibrated to compensate the external oscillator’s
accuracy offset. STC5428 also allow users to pro-
gram and manipulate the holdover history accumula-
tors.
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2 differential clock outputs (LVPECL or LVDS) CLK1
and CLK2, 6 LVCMOS clock outputs CLK3 to CLK8
(LVCMOS), one CLK8K and one CLK2K frame pulse
clock outputs (LVCMOS). CLK1~CLK8 can be
derived from synthesizer G₁~G₈ through T0 path,
respectively, in which CLK3~CLK8 can also be
derived from synthesizer F through T0 path or synthe-
sizer G_T4 through T4 path. See Figure 1 for functional
details. Frequency of clock outputs CLK1~CLK8 is
programmable by programing frequency of the asso-
ciated synthesizer from 1MHz up to 156.25MHz, in
1kHz steps. Each of the synthesizers has different
default frequency value. The STC5428 allows the
user to program the phase skew of each clock syn-
thesizer, up and down 50ns in roughly 0.024ns step
to adjust the phase of clock outputs.
Phase Synchronization
In synchronized mode, the phase relationship
between the selected reference input and the clock
output may be phase arbitrary or frame phase align
for T0 timing generator. For timing generator T4, the
phase relationship is only phase arbitrary. Zero frame
phase relationship is produced for T0 timing genera-
tor by programming as frame phase align mode.
Switching to a new reference input may expect a lon-
ger pull-in process in this mode. On the other hand,
programming as arbitrary mode, an arbitrary phase
relationship incorporates phase rebuild on reference
input switching to minimize the downstream clock’s
phase transient. In this scenario, the STC5428 can
provide hit-less switching if both reference inputs are
traced to the same clock source (e.g., PRC). The
STC5428 may accept external frame reference to
achieve frame alignment in frame phase align mode.
The frame reference and the frame edge, and frame
phase alignment mode may be configured indepen-
dently for each individual reference input.
A maximum frequency ramp may be programmed to
minimize the ramp of fractional frequency offset
changing in the case that the new selected reference
is not traced to the same source. This feature
restrains the frequency transient which may cause
the pull-out-of-lock of the downstream network ele-
ments.
Frame pulse clock synthesizer F generates frame
pulse clock Frame8K/Frame2K at frequency of 8kHz/
2kHz and a proprietary composite signal which car-
ries 8kHz clock, 2kHz frame, and the selected refer-
ence information. The duty-cycle of Frame8K and
Frame2K is programmable. Clock outputs CLK8K
and CLK2K are directly driven from Fram8K and
Frame2K.
Redundant Designs
Timing generator T0 supports master/slave and
multiple-master operation for redundant applications
to allow system protection against the failure of the
single unit.
In master/slave configuration, the slave unit phase-
locks and frame aligns (8kHz or 2kHz) to the cross-
reference from the master unit, using highest avail-
able loop bandwidth and ignores any frequency ramp
protection. The phase of slave’s clock outputs may be
adjusted up and down 3.2us, in 0.1ns step, to
compensate for the propagation and re-transmission
delay of the cross-couple path. This will then mini-
mize the phase hits to the downstream devices result-
ing from master/slave switches.
In multiple-master configuration, all units work as
masters and lock to the same reference input in paral-
lel. With the help of frame phase align mode and the
extra frame edge, clock outputs of all the units may
keep in frame phase alignment. No phase compensa-
Page 19 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014