STC5428 Datasheet, PDF (12/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Addr
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x4A
Reg Name
Device_Holdover_History
Long_Term_Accu_History
Short_Term_Accu_History
User_Specified_History
History_Ramp
Ref_Priority_Table
PLL_Status
Holdover_Accu_Flush
PLL_Event_Out
PLL_Event_In
EX_SYNC_Edge_Config
Slave_Frame_Align
Master_Frame_Align
Master_Slave_Selection_mode
Synth_Index_Select
STC5428
Synchronous Clock for SETS
DATASHEET
Table 5: Register Map
Bits
31-0
Type
Description
R Device Holdover History
31-0
R Long term Accumulated History
31-0
R Short term Accumulated History
31-0 R/W User programmed holdover history
7-0
47-0
R/W Control long term history and short term history accumulation band-
width and the locking stage’s frequency ramp control
R/W REF1-12 selection priority
7-0
0
7-0
7-0
0
3-0
47-0
R PLL status: SYNC, LOS, LOL, OOP, SAP, FEE, DHT, HHA
W Flush the long-term history or both the long-term history and the
device holdover history
R/W PLL event out (Reserved)
R/W PLL event in: Relock
R/W Select framing edge for EX_SYNC (falling or rising edge)
R/W Select cross ref source and frame edge for slave T0 timing genera-
tor
R/W T0 timing generator selects the frame phase alignment and frame
alignment working manner in master mode. Not for T4 timing gener-
ator.
0
R/W Determine ways to select the T0 master/slave mode: Hardware pin
select or register select.
3-0 R/W Determine which synthesizer is selected for setting frequency value
at register Synth_Freq_Value and adjusting phase skew at registers
Synth_Skew_Adj
Page 12 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014