STC5428 Datasheet, PDF (11/66 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Register Map
STC5428
Synchronous Clock for SETS
DATASHEET
Table 5: Register Map
Addr
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F ⁶
0x20
0x21
0x22
0x23
0x24
Reg Name
Chip_ID, 0x00 (R)
Chip_Rev
Chip_Sub_Rev
T0_M/S_Sts
T0_Slave_Phase_Adj
Fill_Obs_Window
Leak_Obs_Window
Bucket_Size
Assert_Threshold
De_Assert_Threshold
Freerun_Cali
Disqualification_Range
Qualification_Range
Qualification_Soaking_Time
Ref_Index_Selector
Ref_Info
Ref_Activity
Ref_Qual
Interrupt_Event_Status
Interrupt_Event_Enable
Interrupt_Config
Hard-Wired_Switch_Pre_Selections
SRCSW_Status
T0/T4_Tag_Select
Control_Mode
Loop_Bandwidth
Auto_Elect_Ref
Manual_Select_Ref
Selected_Ref
Bits
15-0
7-0
7-0
0
15-0
3-0
3-0
5-0
5-0
5-0
10-0
9-0
9-0
5-0
3-0
15-0
12-0
11-0
7-0
7-0
1-0
7-0
0
0
7-2
7-0
3-0
3-0
3-0
Type
R Chip ID = 0x5428
Description
R Chip revision number
R Chip sub-revision number
R Indicates pin MC/SL state when the selection of T0 master/slave
mode is hardware select using pin MC/SL;
R/W Selects either master or slave mode for T0 when the selection of T0
master/slave mode is register select
R/W T0 slave phase adjust, 2’s complement, step in 0.1ns
R/W Activity monitor: Leaky bucket fill observation window
R/W Activity monitor: Leaky bucket leak observation window
R/W Activity monitor: Leaky bucket size
R/W Activity monitor: Leaky bucket alarm assert threshold
R/W Activity monitor: Leaky bucket alarm de-assert threshold
R/W Freerun calibration, 2’s complement, -102.4 to +102.3ppm, step in
0.1ppm
R/W Reference disqualification range, 0 ~102.3ppm. The value is also
specified as pull-in range
R/W Reference qualification range, 0 ~102.3ppm.
R/W
R/W
R
R
Reference qualification soaking time, 0 ~63s
Select a reference input to access the register Ref_Info and
Ref_Acceptable_Freq.
Frequency offset and frequency info of the reference selected by
register Ref_Index_Selector
Reference activity for reference 1 to 12 and cross ref
R Reference 1 ~ 12 qualification
R/W Interrupt events
R/W Selects which of interrupt events will assert pin EVENT_INTR
R/W Pin EVENT_INTR configuration and idle mode
R/W Pre-selected reference number 1 and reference number 2 for hard-
wired manual switch mode
R Indicates the status of pin SRCSW
R/W Selects registers between T0 and T4 for register 0x20 - 0x3F
R/W _{Holdover history usage, Revertive, Manual/Auto, OOP, Slave inherit,}
SRCSW
R/W Loop bandwidth selection
R Indicates the reference elected by auto reference elector
R/W The reference specified by users for manual selection mode
R Indicates the PLL current selected reference
Page 11 of 66
Preliminary
Rev: 0.2
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: April 3, 2014