AK7755EN_16 Datasheet, PDF (85/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
2. Microphone Input Gain
The AK7755 has a microphone gain amplifier. L and R channel gains can be set independently by
MGNL[3:0] bits (CONT12: D3-D0) and MGNR[3:0] bits (CONT12: D7-D4). Input impedance is typ.
20k. This gain amplifier executes zero cross detection when changing the gain by setting MICLZCE bit
(CONT1A: D0) = “1” / MICRZCE bit (CONT1A: D1) = “1”. Zero cross detection is executed on L and
R channels independently. Timeout period of the zero cross detection is 16ms. When MICLZCE bit =
“0” / MICRZCE bit = “0”, zero cross detection is not performed and the volume is changed immediately
when register is written.
When writing to MGNL3-0/MGNR3-0 bits continually, take an interval of zero crossing timeout periods
or more. If the MGNL3-0/MGNR3-0 bits are changed before zero crossing, the volume of Lch and Rch
may differ. When the volume that is same as the present is set, the zero crossing counter is not reset and
timeout according to the previous writing timing.
Zero Crossing Timeout
When MICLZCE bit = “1” / MICRZCE bit = “1”, the Lch/Rch volume level are changed independently
by zero crossing detection or zero crossing timeout.
fs Zero cross Timeout Period
48kHz
16ms
Mode
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MGNL[3]
MGNR[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MGNL[2] MGNL[1]
MGNR[2] MGNR[1]
MGNL[0]
MGNR[0]
Input Gain
0
0
0
0dB
0
0
1
2dB
0
1
0
4dB
0
1
1
6dB
1
0
0
8dB
1
0
1
10dB
1
1
0
12dB
1
1
1
14dB
0
0
0
16dB
0
0
1
18dB
0
1
0
21dB
0
1
1
24dB
1
0
0
27dB
1
0
1
30dB
1
1
0
33dB
1
1
1
36dB
Table 2. Microphone Input Gain
(default)
3. Analog DRC (ADRC)
The microphone input gain can be set by DSP programs with the AK7755. This function is enabled by
setting ADRCRE bit = “1”/ADRCLE bit = “1” (CONT1A: D3/D2). In this setting, control registers
MGNL[3:0] and MDNR[3:0] bits (CONT12) are not valid. By reading AMGNL[3:0] (CONT1B:
D3-D0) / AMGNR[3:0] (CONT1B: D7-D4) bits, gain settings can be downloaded externally.
When MICLZCE bit = “1”/MICRZCE bit = “1”, the Lch/Rch volume level are changed independently
by zero crossing detection or zero crossing timeout. Please refer to the AK7755 programing manual for
DSP programs.
014006643-E-00
- 85 -
2014/10