AK7755EN_16 Datasheet, PDF (26/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
■ System Clock
9. Functional Description
Master/Slave mode switching, clock source pin select for internal master clock (MCLK) generating clock
(ICLK), and ICLK frequency change are controlled by CKM [2:0] clock mode select bits. CKM[2:0] bits
can only be set during clock reset.
CKM CKM Master
mode [2:0] Slave
ICLK Sampling Frequency Input pin(s) required for
Source fs (Note 41)
system clock
Use of
crystal
oscillator
0
000 Master
XTI DFS[2:0]bits
XTI(12.288MHz)
Available
1
001 Master
XTI DFS[2:0]bits
XTI(18.432MHz)
Available
2
010 Slave
XTI DFS[2:0]bits
XTI(12.288MHz), BICK,
Not
LRCK
Available
3
011 Slave BICK DFS[2:0]bits
BICK, LRCK
Not
Available
5
101 Slave BICK Fs=16kHz Fixed
BICK, LRCK(fs=8kHz)
Not
Available
Note 41. The sampling frequency is set by DFS[2:0] bits (CONT00). The BICK frequency is set by
BITFS[1:0] bits.
Note 42. In CKM mode 2, XTI, BICK and LRCK must be synchronized but the phase is not critical.
Note 43. CKM mode5 is the mode that operates DSP, ADC and DAC by 16kHz sampling frequency when
LRCK sampling frequency is 8kHz. The BICK sampling frequency for LRCK is set by
BITFS[1:0] bits.
1. Relationship between MCLK Generating Clock (ICLK) and MCLK
CKM mode 0/1/2
CKM mode 3/5
XTI Pin
ICLK
(MCLK Source)
Divider
REFCLK
PLL
BICK Pin ^ICLK
Divider
REFCLK
PLL
(MCLK Source)
Figure 16. Relation Ship between ICLK and MCLK
MCLK
MCLK
2. Sampling Frequency Select
FS mode
0
1
2
3
4
5
6
7
DFS[2:0]
000
001
010
011
100
101
110
111
fs: Sampling Frequency
8kHz
12kHz (11.025kHz)
16kHz
24kHz (22.05kHz)
32kHz
48kHz (44.1kHz)
96kHz (88.2kHz)
N/A
014006643-E-00
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2014/10