AK7755EN_16 Datasheet, PDF (76/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
DSPRESETN bit= “1”
CSN
SCLK
SI
don’tcare Command _{Address DATA0}
(L/H)
Code
DATA1
DATAn-1 DATAn
(Ex.) When # of DATA is 4
CRAM Command Code 0x83
OFREG Command Code 0x93
don’tcare
(L/H)
RDY = “H”
CRAM 0x80(# of DATA: 1)~0x8F(# of DATA: 16)
OFREG 0x90(# of DATA: 1)~0x9F(# of DATA: 16)
Figure 55. CRAM/OFREG Write Preparation (SPI)
DSPRESTN bit= “1”
CSN
SCLK
don’t care
SI
(L/H)
Hi-Z or Low
SO
0x24
RDY= “H”
don’t care
(L/H)
Address DATA DATA DATA DATA DATA
Figure 56. CRAM/OFREG Write Preparation Confirm (SPI)
DSPRESETN bit= “1”
CSN
SCLK
SI
don’tcare
(L/H)
Command
CRAM0xA4, OFREG0xA2
RDY
00000000
00000000
max 400ns
RDYLG (Note 52)
Figure 57. CRAM/OFREG Write (SPI)
Note 51. If the DSP program is designed to refer all coefficients which may be changed by an external
microcontroller, RDY signal rises to high within 2LRCK after a writing command. No further
access to DSP is permitted until this write operation is completed. However, while the CSN pin is
“L” level, RDY signal keeps “L” level.
014006643-E-00
- 76 -
2014/10