AK7755EN_16 Datasheet, PDF (20/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
2. Power Down
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V)
Parameter
Symbol
min
typ
max
Unit
PDN Pulse Width (Note 34) tRST
600
ns
Note 34. The PDN pin must be set “L” when power up the AK7755.
PDN
tRST
VIL
Figure 5. Reset Timing
3. Serial Data Interface
SDIN1, SDIN2, SDOUT1, SDOUT2, SDOUT3
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol min typ max Unit
Slave Mode
Delay Time from BICK “↑” to LRCK (Note 35)
tBLRD 20
ns
Delay Time from LRCK to BICK “↑” (Note 35)
tLRBD 20
ns
Serial Data Input Latch Setup Time
tBSIDS 20
ns
Serial Data Input Latch Hold Time
tBSIDH 20
ns
Delay Time from LRCK to Serial Data Output (Note 36)
tLRD
20 ns
Delay Time from BICK “↓” to LRCK Output (Note 37)
tBSOD
20 ns
Master Mode
BICK Frequency
fBCLK
32, 48
64, 256
fs
BICK Duty Cycle
50
%
Delay Time from BICK “↓” to LRCK (Note 37)
tMBL -12
12 ns
Serial Data Input Latch Setup Time
tBSIDS 20
ns
Serial Data Input Latch Hold Time
tBSIDH 20
ns
Delay Time from LRCK to Serial Data Output (Note 36)
tLRD
20 ns
Delay Time from BICK “↓” or “↑”to LRCK Output (Note 37) tBSOD
20 ns
SDINn → SDOUTn (n=1, 2)
Delay Time from SDINn to SDOUTn Output
tIOD
60 ns
Note 35. BICK edge must not occur at the same time as LRCK edge.
If BICK polarity was inverted, the counting edge of BICK will be “↓”.
Note 36. Except I²S.
Note 37. When the polarity of BICK1 is inverted, delay time is from BICK1 “↑”.
SDOUT
Nn=n1,2,3
SDINn
n=1,2
50%TVDD
tIOD
VIH
D _VIH
D^VIL
D
Figure 6. Serial Interface Delay Time from SDINn to SDOUTn Output
014006643-E-00
- 20 -
2014/10