AK7755EN_16 Datasheet, PDF (78/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
7-4. RAM Reading Timing during System Reset
Read Program RAM (PRAM), Coefficient RAM (CRAM), Offset REG (OFREG) and Accelerator
Coefficient RAM (ACRAM) during System Reset in the order of the input Command code and the
Address. After writing the Command, the data comes out from the SO pin synchronous with falling
edge of SCLK. (The SI pin input data is “Don’t care”) When reading Data at consecutive address
locations, continue to input SCLK as is.
DSPRESETN bit
CSN
SCLK
don’t care
SI ^(L/H)
Hi-Z or Low
SO
Command
Address
don’t care
(L/H)
Echo Back Output DATA DATA
DATA
DATA
DATA
RDY = “H”
Figure 60. RAM Reading at Consecutive Address (SPI)
7-5. RAM Reading Timing during System Reset and RUN
Write a command code, to read control registers, device identification code, CRC result and error
status during RUN time or system reset state. After completing a Command code write, the data comes
out from the SO pin synchronous with falling edge of SCLK. (The SI pin input data is “Don’t care”)
DSPRSTN bit
CSN
SCLK
SI
don’tcare
(L/H)
Hi-Z or Low
SO
RDY = “H”
Command
Address
don’tcare
(L/H)
Echo Back Output
DATA
Figure 61. AM Reading during System Reset/RUN (SPI)
014006643-E-00
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