AK7755EN_16 Datasheet, PDF (19/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
■ Switching Characteristics
1. System Clock
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol
min
typ
max
Unit
a) with a Crystal Oscillator:
CKM[2:0]bits=0h
fXTI
11.2896
12.288
MHz
CKM[2:0]bits=1h
fXTI
16.9344
18.432
MHz
b) with an External Clock
Duty Cycle
40
50
60
%
CKM[2:0]bits=0h,2h
fXTI
11.0
11.2896
12.288
12.4 MHz
CKM[2:0]bits=1h
fXTI
16.5
16.9344
18.432
18.6 MHz
LRCK Frequency
(Note 32)
fs
8
48
96
kHz
BICK Frequency
(Note 33)
TDM256 bit = “0” High Level Width tBCLKH
64
(Normal Interface) Low Level Width tBCLKL
64
Frequency
fBCLK
0.23
TDM256 bit = “1” High Level Width tBCLKH
32
(TDM Interface)
Low Level Width tBCLKL
32
Frequency
fBCLK
1.8
3.072
12.288
ns
ns
6.2
MHz
ns
ns
12.3
MHz
Note 32. RCK frequency and sampling rate (fs) should be the same.
Note 33. When BICK is the source of the master clock, it should be synchronized to LRCK and have stable
frequency.
1/fXTI
1/fXTI
tXTI=1/fXTI
XTI
VIH
VIL
LRCK
BICK
1/fs
1/fs
ts=1/fs
VIH
VIL
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
VIL
tBCLKH tBCLKL
Figure 4. System Clock Timing
014006643-E-00
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2014/10