AK7755EN_16 Datasheet, PDF (55/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
■ LDO (Internal Circuit Drive Regulator)
The AK7755 has a regulator for driving internal digital circuits (LDO). When using the LDO, the LDOE
pin must be fixed to “H” and connect a 1μF (±30%) capacitor between the AVDRV pin and the VSS pin.
The LDO starts operation by releasing power-down mode, and control register write/read can be made 1ms
after the power-down release.
The AK7755 has an overcurrent protection circuit to avoid abnormal heat of the device that is caused by a
short of the AVDRV pin to VSS and etc., and an overvoltage protection circuit to protect from exceeded
voltage when the voltage to the AVDRV pin gets too high. When these protection circuits perform, internal
circuits are powered down and the STO pin outputs “L”. The internal circuit will not return to a normal
operation until being reset by the PDN pin after removing the problems.
TVDD,AVDD
LDOE (pin)
AVDRV (pin)
PDN (pin)
STO (pin)
SI(SPI),SDA(I2C)
CKRESETN bit (Reg.)
DSPRESETN bit(Reg.)
CRESETN bit(Reg.)
XTI,BICK (pin)
Internal PLLCLK
(Internal Master Clock)
CONT Reg. Setting
Clock Stabilization
DSP Program
Power OFF 600ns(min) 1ms(min)
Before PLL stable oscillation
access is not permitted
(10ms)
Command code and DSP
Program download
（No time limitation）
Figure 28. Power-up Sequence 5
(With LDO (LDOE pin = “H”), No downloading from EEPROM)
■ Power-down Sequence
The AK7755 should be powered down when the PDN pin = “L”. Stop external clocks during this
power-down state and then OFF the power supplies. Do not input external clocks when the power supplies
are off (a current will flow through protection diodes). AVDD and TVDD must be powered down after
DVDD when DVDD is supplied externally (LDOE pin = “L”). In this case, the power-down sequence
between AVDD and TVDD is not critical.
TVDD,AVDD
DVDD
PDN(pin)
Power OFF
Figure 29. Power-down Sequence
014006643-E-00
- 55 -
2014/10