AK7755EN_16 Datasheet, PDF (58/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
5. System Reset
System reset is defined as when CRESETN bit (CONT0F: D3) = “0” and DSPRESETN bit (CONT0F:
D2) = “0” after clock reset is released (CKRESETN bit (CONT01: D0) = “1”). PRAM and CRAM
downloading should be executed in this state. PRAM and CRAM accessing of the AK7755 should be
made when PLL oscillation is stabilized after clock reset release (take a 10ms interval or confirm “H”
level output of PLLLOCK signal from the STO pin).
System reset is released when either CODEC reset (CRESETN bit) or DSP reset (DSPRESETN bit) is
released (“0” → “1”) after DSP programs and coefficient data are transmitted. Then the AK7755 starts
generating necessary clocks for ADC, DAC and DSP operations. A system reset image is shown below.
CRESETN bit
DSPRESETN bit
SRESETN
Figure 31. System Reset Structure
In slave mode, the AK7755 starts operation in synchronization of an LRCK rising edge (falling edge in
I²S mode) when system reset is released. If the LRCK is stopped or the LRCK phase is shifted more
than 1/4fs, the AK7755 becomes the system reset state automatically. In this case, the system reset state
is released if the LRCK is input again.
■ RAM Clear
The AK7755 has a RAM clear function. After system reset release (during RUN), data RAM and delay
RAM are cleared by “0” (RAM clear). The internal PLL must have a stable oscillation before system
reset release. The required time to clear RAM is 400µs.
In the RAM clear sequence, it is possible to send commands to the DSP. (DSP is stopped during RAM
clear sequence. The sent command is accepted automatically after this sequence is completed.)
PDN (pin)
DSPRESETN bit
RAM Clear
DSP Start
RAM Clear Period
Figure 32. RAM Clear Sequence
DSP Program
Operation Start
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