AK7755EN_16 Datasheet, PDF (24/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
5. I²C-BUS Interface
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol min typ max Unit
I2C Timing
SCL clock frequency
fSCL
400 kHz
Bus Free Time Between Transmissions
tBUF
1.3
s
Start Condition Hold Time (prior to first Clock pulse)
tHD:STA 0.6
s
Clock Low Time
tLOW
1.3
s
Clock High Time
tHIGH
0.6
s
Setup Time for Repeated Start Condition
tSU:STA 0.6
s
SDA Hold Time from SCL Falling
tHD:DAT 0
0.9 s
SDA Setup Time from SCL Rising
tSU:DAT 0.1
s
Rise Time of Both SDA and SCL Lines
tR
0.3 s
Fall Time of Both SDA and SCL Lines
tF
0.3 s
Setup Time for Stop Condition
tSU:STO 0.6
s
Pulse Width of Spike Noise Suppressed By Input Filter
tSP
0
50 ns
Capacitive load on bus
Cb
400 pF
SDA
tBUF
tLOW tR
tHIGH tF
SCL
tHD:STA
Stop Start
tHD:DAT
tSU:DAT tSU:STA
Start
Figure 14. I²C BUS Interface Timing
VIH
VIL
tSP
VIH
VIL
tSU:STO
Stop
6. Digital Microphone Interface
(AVDD=3.0~3.6V, TVDD=1.7~3.6V, DVDD=1.14~1.3V, AVSS=DVSS=0V, Ta= -40C~85C;
CL=100pF)
Parameter
Symbol
min
typ
max
DMDAT1, DMDAT2
Serial Data Input Latch Setup Time tDMDS
50
Serial Data Input Latch Hold Time tDMDH
0
DMCLK1, DMCLK2
Clock Frequency (Note 40)
fDMCK
0.5
64fs
6.2
Duty Cycle
dDMCK
40
50
60
Rise Time
tDMCKR
10
Fall Time
tDMCKF
10
Note 40. Clock frequency is determined by the sampling rate (fs) selected by DFS[2:0] bits.
Unit
ns
ns
MHz
%
ns
ns
014006643-E-00
- 24 -
2014/10