AK7755EN_16 Datasheet, PDF (74/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
6-6. Read Operation during RUN
1. CRAM Write Preparation Read (during RUN)
Field
Write data
Readout data
(1) COMMAND Code 0x24
(2) ADDRESS1
A15~A8
(3) ADDRESS2
A8~A0
(4) DATA1
D23~D16
(5) DATA2
D15~D8
(6) DATA3
D7~D0
2. OFREG Write Preparation Read (during RUN)
Field
Write data
Readout data
(1) COMMAND Code 0x24
(2) ADDRESS1
A15~A8
(3) ADDRESS2
A8~A0
(4) DATA1
00000000
(5) DATA2
D15~D8
(6) DATA3
D7~D0
3. MIR1/2/3/4 Read (during RUN)
Field
Write data
Readout data
(1) COMMAND Code 0x76(MIR1)
0x78(MIR2)
0x7A(MIR3)
0x7C(MIR4)
(2) DATA1
D27~D20
(3) DATA2
D19~D12
(4) DATA3
D11~D4
(5) DATA4
D3 D2 D1 D0 (flag3) (flag2) (flag1) (flag0)
Note 48. Data is valid only when all flags are zero.
7. Timing
7-1. RAM Writing Timing during System Reset
Write to Program RAM (PRAM), Coefficient RAM (CRAM), Offset REG (OFREG) and Accelerator
Coefficient RAM (CRAM) during system reset in the order of command code, address and data. The
PRAM start address is fixed to 0h. When writing the data to consecutive address locations, continue to
input data only. PRAM address is incremented by 1 automatically.
DSPRESETN bit
CSN
SCLK
SI
don’t care
(L/H)
Command
Address
DATA DATA
DATA
DATA
DATA
don’t care
(L/H)
RDY = “H”
Figure 53. Writing to RAM at Consecutive Address Locations (SPI)
014006643-E-00
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