AK7755EN_16 Datasheet, PDF (44/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
CONT0F: Reset Settings, Lineout and Digital MIC2 Rch Power Managements
W R Name D7 D6 D5 D4
D3
D2
D1
D0
Default
CFh 4Fh CONT0F 0 0 PML1 LRDETN CRESETN DSPRESETN PMAD2R DLRDY 00h
D5: PMLI Line-in Power Management
0: Power-down (default)
1: Normal Operation
D4: LRDETN Slave Mode Automatic System Reset Setting
0: LRCK Detect ON (default)
1: LRCK Detect OFF
When this bit is “0”, if the LRCK is stopped or the LRCK phase is shifted more than 1/4fs, the
AK7755 enters system reset state automatically.
D3: CRESETN CODEC Reset N
0: CODEC Reset (default)
1: CODEC Reset Release
CODEC means the ADC and the DAC.
D2: DSPRESETN DSP Reset N
0: DSP Reset (default)
1: DSP Reset Release
The AK7755 is in system reset state when CRESETN bit = “0” and DSPRESETN bit = “0”.
D1: PMAD2R Power Managements of ADC2 Rch (only when using digital microphone)
0: Power-down (default)
1: The AK7755 enters normal operation after releasing CODEC Reset (CRESETN bit = “1”).
D0: DLRDY DSP Download Ready
0: Normal Operation (default)
1: Program Downloading
DSP programs and coefficient data can be downloaded by setting this bit to “1” during clock reset
(CKRESETN bit = “0”) or when the main clock is stopped. This bit must be set to “0” after finishing
the downloading.
Write “0” into the “0” registers.
014006643-E-00
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2014/10