AK7755EN_16 Datasheet, PDF (22/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
4. SPI Interface
4-1. Clock Reset (CKRESTN bit = “0”)
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol min
typ
max
Unit
Microcontroller Interface Signal
SCLK Frequency
fSCLK
3.5
MHz
SCLK Low Level Width
tSCLKL 120
ns
SCLK High Level Width
tSCLKH 120
ns
Microcontroller → AK7755
CSN High Level Width
tWRQH 300
ns
Time from CSN “↑” to PDN “↑”
tRST
360
ns
Time from PDN“↑” to CSN “↓”
tIRRQ
1
ms
Time from RQN“↓” to SCLK“↓”
tWSC
360
ns
Time from SCLK“↑” to CSN“↑”
tSCW
480
ns
SI Latch Setup Time
tSIS
120
ns
SI Latch Hold Time
tSIH
120
ns
AK7755 → Microcontroller
SO Output Delay Time from SCLK “↓”
tSOS
120
ns
SO Output Hold Time from SCLK “↑”
(Note 38)
tSOH
120
ns
Note 38. Except when input the eighth bit of the command code.
4-2. PLL Clock (CKRESTN bit = “1”)
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol min
typ
max
Unit
Microcontroller Interface Signal
SCLK Frequency
fSCLK
7
MHz
SCLK Low Level Width
tSCLKL 60
ns
SCLK High Level Width
tSCLKH 60
ns
Microcontroller → AK7755
CSN High Level Width
tWRQH 150
ns
Time from CSN “↑” to PDN “↑”
tRST
180
ns
Time from PDN“↑” to CSN “↓”
tIRRQ
1
ms
Time from RQN“↓” to SCLK“↓”
tWSC
150
ns
Time from SCLK“↑” to CSN“↑”
tSCW
240
ns
SI Latch Setup Time
tSIS
60
ns
SI Latch Hold Time
tSIH
60
ns
AK7755 → Microcontroller
SO Output Delay Time from SCLK “↓”
tSOS
60
ns
SO Output Hold Time from SCLK “↑”
(Note 38)
tSOH
60
ns
Note 39. It takes 10ms at maximum until PLL is locked, after setting CKRESTN bit to “1” from “0”.
014006643-E-00
- 22 -
2014/10